[PATCH v2 2/2] arm64: dts: qcom: sm8350: Add thermal zones and throttling support

2021-03-23 Thread Robert Foss 
sm8350 has 29 thermal sensors split across two tsens controllers. Add
the thermal zones to expose them and wireup the cpus to throttle their
frequencies on crossing passive temperature thresholds.

Signed-off-by: Robert Foss 
Reviewed-by: Vinod Koul 
---

Changes since v1:
 - Vinod: Remove comment

Changes since v2:
 - Vinod: Add r-b
 - Konrad: Use lower case hex addresses
 - Really remove comments


 arch/arm64/boot/dts/qcom/sm8350.dtsi | 826 +++
 1 file changed, 826 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 4abdba78cec1..3b53066285ce 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
interrupt-parent = <&intc>;
@@ -46,6 +47,7 @@ CPU0: cpu@0 {
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_0: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -62,6 +64,7 @@ CPU1: cpu@100 {
enable-method = "psci";
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_100: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -75,6 +78,7 @@ CPU2: cpu@200 {
enable-method = "psci";
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_200: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -88,6 +92,7 @@ CPU3: cpu@300 {
enable-method = "psci";
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_300: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -101,6 +106,7 @@ CPU4: cpu@400 {
enable-method = "psci";
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
+   #cooling-cells = <2>;
L2_400: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -114,6 +120,7 @@ CPU5: cpu@500 {
enable-method = "psci";
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
+   #cooling-cells = <2>;
L2_500: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -128,6 +135,7 @@ CPU6: cpu@600 {
enable-method = "psci";
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
+   #cooling-cells = <2>;
L2_600: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -141,6 +149,7 @@ CPU7: cpu@700 {
enable-method = "psci";
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 2>;
+   #cooling-cells = <2>;
L2_700: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -682,6 +691,28 @@ pdc: interrupt-controller@b22 {
interrupt-controller;
};
 
+   tsens0: thermal-sensor@c222000 {
+   compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
+   reg = <0 0x0c263000 0 0x1ff>, /* TM */
+ <0 0x0c222000 0 0x8>; /* SROT */
+   #qcom,sensors = <15>;
+   interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+<&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-names = "uplow", "critical";
+   #thermal-sensor-cells = <1>;
+   };
+
+   tsens1: thermal-sensor@c223000 {
+   compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
+   reg = <0 0x0c265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x8>; /* SROT */
+   #qcom,sensors = <14>;
+

Re: [PATCH v2 2/2] arm64: dts: qcom: sm8350: Add thermal zones and throttling support

2021-03-23 Thread Robert Foss 
Hey Konrad,

Thanks for the review!


On Mon, 22 Mar 2021 at 18:27, Konrad Dybcio
 wrote:
>
> Hi!
>
>
> > + tsens0: thermal-sensor@c222000 {
> > + compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
> > + reg = <0 0x0C263000 0 0x1ff>, /* TM */
> > +   <0 0x0C222000 0 0x8>; /* SROT */
>
> Please use lowercase hex

Ack

>
>
> > + tsens1: thermal-sensor@c223000 {
> > + compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
> > + reg = <0 0x0C265000 0 0x1ff>, /* TM */
> > +   <0 0x0c223000 0 0x8>; /* SROT */
>
> Ditto

Ack

>
>
> > + trips {
> > + cpu0_alert0: trip-point0 {
> > + temperature = <9>;
> > + hysteresis = <2000>;
> > + type = "passive";
> > + };
> > +
> > + cpu0_alert1: trip-point1 {
> > + temperature = <95000>;
> > + hysteresis = <2000>;
> > + type = "passive";
>
> Shouldn't this be "hot"? Possibly ditto for all cpu*alert1-labeled nodes.

I based this patch on the upstream DTS for sm8250 & sdm845, and this
is what they use. However, if you think it is incorrect I'm happy to
do a little digging.

>
>
> > + };
> > +
> > + cpu0_crit: cpu_crit {
> > + temperature = <11>;
> > + hysteresis = <1000>;
> > + type = "critical";
> > + };
> > + };
>
> These values seem, err.. scorching hot.. Are they alright?

I agree :) This is what the vendor ships in their downstream DTS.

>
>
>
> > + // TODO: What is the NSP subsystem?
> Please use C-style comments (/* foo */)

Removing comment.

Re: [PATCH v2 2/2] arm64: dts: qcom: sm8350: Add thermal zones and throttling support

2021-03-22 Thread Konrad Dybcio 
Hi!


> + tsens0: thermal-sensor@c222000 {
> + compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
> + reg = <0 0x0C263000 0 0x1ff>, /* TM */
> +   <0 0x0C222000 0 0x8>; /* SROT */

Please use lowercase hex


> + tsens1: thermal-sensor@c223000 {
> + compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
> + reg = <0 0x0C265000 0 0x1ff>, /* TM */
> +   <0 0x0c223000 0 0x8>; /* SROT */

Ditto


> + trips {
> + cpu0_alert0: trip-point0 {
> + temperature = <9>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu0_alert1: trip-point1 {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "passive";

Shouldn't this be "hot"? Possibly ditto for all cpu*alert1-labeled nodes.


> + };
> +
> + cpu0_crit: cpu_crit {
> + temperature = <11>;
> + hysteresis = <1000>;
> + type = "critical";
> + };
> + };

These values seem, err.. scorching hot.. Are they alright?



> + // TODO: What is the NSP subsystem?
Please use C-style comments (/* foo */)




Konrad

Re: [PATCH v2 2/2] arm64: dts: qcom: sm8350: Add thermal zones and throttling support

2021-03-22 Thread Vinod Koul 
On 22-03-21, 11:04, Robert Foss wrote:
> sm8350 has 29 thermal sensors split across two tsens controllers. Add
> the thermal zones to expose them and wireup the cpus to throttle their
> frequencies on crossing passive temperature thresholds.

Reviewed-by: Vinod Koul 

-- 
~Vinod

[PATCH v2 2/2] arm64: dts: qcom: sm8350: Add thermal zones and throttling support

2021-03-22 Thread Robert Foss 
sm8350 has 29 thermal sensors split across two tsens controllers. Add
the thermal zones to expose them and wireup the cpus to throttle their
frequencies on crossing passive temperature thresholds.

Signed-off-by: Robert Foss 
---


Changes since v1:
 - Vinod: Remove comment


 arch/arm64/boot/dts/qcom/sm8350.dtsi | 829 +++
 1 file changed, 829 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi 
b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 4abdba78cec1..424887652f47 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
interrupt-parent = <&intc>;
@@ -46,6 +47,7 @@ CPU0: cpu@0 {
enable-method = "psci";
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_0: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -62,6 +64,7 @@ CPU1: cpu@100 {
enable-method = "psci";
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_100: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -75,6 +78,7 @@ CPU2: cpu@200 {
enable-method = "psci";
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_200: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -88,6 +92,7 @@ CPU3: cpu@300 {
enable-method = "psci";
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
+   #cooling-cells = <2>;
L2_300: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -101,6 +106,7 @@ CPU4: cpu@400 {
enable-method = "psci";
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 1>;
+   #cooling-cells = <2>;
L2_400: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -114,6 +120,7 @@ CPU5: cpu@500 {
enable-method = "psci";
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 1>;
+   #cooling-cells = <2>;
L2_500: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -128,6 +135,7 @@ CPU6: cpu@600 {
enable-method = "psci";
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
+   #cooling-cells = <2>;
L2_600: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -141,6 +149,7 @@ CPU7: cpu@700 {
enable-method = "psci";
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 2>;
+   #cooling-cells = <2>;
L2_700: l2-cache {
  compatible = "cache";
  next-level-cache = <&L3_0>;
@@ -682,6 +691,28 @@ pdc: interrupt-controller@b22 {
interrupt-controller;
};
 
+   tsens0: thermal-sensor@c222000 {
+   compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
+   reg = <0 0x0C263000 0 0x1ff>, /* TM */
+ <0 0x0C222000 0 0x8>; /* SROT */
+   #qcom,sensors = <15>;
+   interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+<&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
+   interrupt-names = "uplow", "critical";
+   #thermal-sensor-cells = <1>;
+   };
+
+   tsens1: thermal-sensor@c223000 {
+   compatible = "qcom,sm8350-tsens", "qcom,tsens-v2";
+   reg = <0 0x0C265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x8>; /* SROT */
+   #qcom,sensors = <14>;
+   interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+<&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
+