Re: [PATCH v2 2/2] drm/panel: simple: Add support BOE nv101wxmn51

2016-12-13 Thread Caesar Wang

在 2016年12月13日 04:22, Stéphane Marchesin 写道:

On Wed, Dec 7, 2016 at 11:26 PM, Caesar Wang  wrote:

10.1WXGA is a color active matrix TFT LCD module using amorphous silicon
TFT's as an active switching devices. It can be supported by the
simple-panel driver.

Read the panel edid information;

EDID MODE DETAILS
 name = 
 pixel_clock = 71900
 lvds_dual_channel = 0
 refresh = 0
 ha = 1280
 hbl = 160
 hso = 48
 hspw = 32
 hborder = 0
 va = 800
 vbl = 32
 vso = 3
 vspw = 5
 vborder = 0
 phsync = +
 pvsync = -
 x_mm = 0
 y_mm = 0
drm_display_mode
 .hdisplay = 1280
 .hsync_start = 1328
 .hsync_end = 1360
 .htotal = 1440
 .vdisplay = 800
 .vsync_start = 803
 .vsync_end = 808
 .vtotal = 832

Signed-off-by: Caesar Wang 
---

Changes in v2:
- fix the vsync_start and vsync_end from the edid.
- change the commit.

  drivers/gpu/drm/panel/panel-simple.c | 31 +++
  1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-simple.c 
b/drivers/gpu/drm/panel/panel-simple.c
index 06aaf79..7c90f16 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -668,6 +668,34 @@ static const struct panel_desc avic_tm070ddh03 = {
 },
  };

+static const struct drm_display_mode boe_nv101wxmn51_mode = {
+   .clock = 71900,
+   .hdisplay = 1280,
+   .hsync_start = 1280 + 48,
+   .hsync_end = 1280 + 48 + 32,
+   .htotal = 1280 + 48 + 32 + 80,
+   .vdisplay = 800,
+   .vsync_start = 800 + 3,
+   .vsync_end = 800 + 3 + 5,
+   .vtotal = 800 + 3 + 5 + 24,
+   .vrefresh = 60,
+};
+
+static const struct panel_desc boe_nv101wxmn51 = {
+   .modes = _nv101wxmn51_mode,
+   .num_modes = 1,

There are two modes in the EDID (there is a downclock one). Can you
add both modes?


Yup, I will add them for next version.
Thanks.

-Caesar


Stéphane


+   .bpc = 8,
+   .size = {
+   .width = 217,
+   .height = 136,
+   },
+   .delay = {
+   .prepare = 210,
+   .enable = 50,
+   .unprepare = 160,
+   },
+};
+
  static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
 .clock = 66770,
 .hdisplay = 800,
@@ -1748,6 +1776,9 @@ static const struct of_device_id platform_of_match[] = {
 .compatible = "avic,tm070ddh03",
 .data = _tm070ddh03,
 }, {
+   .compatible = "boe,nv101wxmn51",
+   .data = _nv101wxmn51,
+   }, {
 .compatible = "chunghwa,claa070wp03xg",
 .data = _claa070wp03xg,
 }, {
--
2.7.4

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Re: [PATCH v2 2/2] drm/panel: simple: Add support BOE nv101wxmn51

2016-12-13 Thread Caesar Wang

在 2016年12月13日 04:22, Stéphane Marchesin 写道:

On Wed, Dec 7, 2016 at 11:26 PM, Caesar Wang  wrote:

10.1WXGA is a color active matrix TFT LCD module using amorphous silicon
TFT's as an active switching devices. It can be supported by the
simple-panel driver.

Read the panel edid information;

EDID MODE DETAILS
 name = 
 pixel_clock = 71900
 lvds_dual_channel = 0
 refresh = 0
 ha = 1280
 hbl = 160
 hso = 48
 hspw = 32
 hborder = 0
 va = 800
 vbl = 32
 vso = 3
 vspw = 5
 vborder = 0
 phsync = +
 pvsync = -
 x_mm = 0
 y_mm = 0
drm_display_mode
 .hdisplay = 1280
 .hsync_start = 1328
 .hsync_end = 1360
 .htotal = 1440
 .vdisplay = 800
 .vsync_start = 803
 .vsync_end = 808
 .vtotal = 832

Signed-off-by: Caesar Wang 
---

Changes in v2:
- fix the vsync_start and vsync_end from the edid.
- change the commit.

  drivers/gpu/drm/panel/panel-simple.c | 31 +++
  1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-simple.c 
b/drivers/gpu/drm/panel/panel-simple.c
index 06aaf79..7c90f16 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -668,6 +668,34 @@ static const struct panel_desc avic_tm070ddh03 = {
 },
  };

+static const struct drm_display_mode boe_nv101wxmn51_mode = {
+   .clock = 71900,
+   .hdisplay = 1280,
+   .hsync_start = 1280 + 48,
+   .hsync_end = 1280 + 48 + 32,
+   .htotal = 1280 + 48 + 32 + 80,
+   .vdisplay = 800,
+   .vsync_start = 800 + 3,
+   .vsync_end = 800 + 3 + 5,
+   .vtotal = 800 + 3 + 5 + 24,
+   .vrefresh = 60,
+};
+
+static const struct panel_desc boe_nv101wxmn51 = {
+   .modes = _nv101wxmn51_mode,
+   .num_modes = 1,

There are two modes in the EDID (there is a downclock one). Can you
add both modes?


Yup, I will add them for next version.
Thanks.

-Caesar


Stéphane


+   .bpc = 8,
+   .size = {
+   .width = 217,
+   .height = 136,
+   },
+   .delay = {
+   .prepare = 210,
+   .enable = 50,
+   .unprepare = 160,
+   },
+};
+
  static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
 .clock = 66770,
 .hdisplay = 800,
@@ -1748,6 +1776,9 @@ static const struct of_device_id platform_of_match[] = {
 .compatible = "avic,tm070ddh03",
 .data = _tm070ddh03,
 }, {
+   .compatible = "boe,nv101wxmn51",
+   .data = _nv101wxmn51,
+   }, {
 .compatible = "chunghwa,claa070wp03xg",
 .data = _claa070wp03xg,
 }, {
--
2.7.4

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Re: [PATCH v2 2/2] drm/panel: simple: Add support BOE nv101wxmn51

2016-12-12 Thread Stéphane Marchesin
On Wed, Dec 7, 2016 at 11:26 PM, Caesar Wang  wrote:
> 10.1WXGA is a color active matrix TFT LCD module using amorphous silicon
> TFT's as an active switching devices. It can be supported by the
> simple-panel driver.
>
> Read the panel edid information;
>
> EDID MODE DETAILS
> name = 
> pixel_clock = 71900
> lvds_dual_channel = 0
> refresh = 0
> ha = 1280
> hbl = 160
> hso = 48
> hspw = 32
> hborder = 0
> va = 800
> vbl = 32
> vso = 3
> vspw = 5
> vborder = 0
> phsync = +
> pvsync = -
> x_mm = 0
> y_mm = 0
> drm_display_mode
> .hdisplay = 1280
> .hsync_start = 1328
> .hsync_end = 1360
> .htotal = 1440
> .vdisplay = 800
> .vsync_start = 803
> .vsync_end = 808
> .vtotal = 832
>
> Signed-off-by: Caesar Wang 
> ---
>
> Changes in v2:
> - fix the vsync_start and vsync_end from the edid.
> - change the commit.
>
>  drivers/gpu/drm/panel/panel-simple.c | 31 +++
>  1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c 
> b/drivers/gpu/drm/panel/panel-simple.c
> index 06aaf79..7c90f16 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -668,6 +668,34 @@ static const struct panel_desc avic_tm070ddh03 = {
> },
>  };
>
> +static const struct drm_display_mode boe_nv101wxmn51_mode = {
> +   .clock = 71900,
> +   .hdisplay = 1280,
> +   .hsync_start = 1280 + 48,
> +   .hsync_end = 1280 + 48 + 32,
> +   .htotal = 1280 + 48 + 32 + 80,
> +   .vdisplay = 800,
> +   .vsync_start = 800 + 3,
> +   .vsync_end = 800 + 3 + 5,
> +   .vtotal = 800 + 3 + 5 + 24,
> +   .vrefresh = 60,
> +};
> +
> +static const struct panel_desc boe_nv101wxmn51 = {
> +   .modes = _nv101wxmn51_mode,
> +   .num_modes = 1,

There are two modes in the EDID (there is a downclock one). Can you
add both modes?

Stéphane

> +   .bpc = 8,
> +   .size = {
> +   .width = 217,
> +   .height = 136,
> +   },
> +   .delay = {
> +   .prepare = 210,
> +   .enable = 50,
> +   .unprepare = 160,
> +   },
> +};
> +
>  static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
> .clock = 66770,
> .hdisplay = 800,
> @@ -1748,6 +1776,9 @@ static const struct of_device_id platform_of_match[] = {
> .compatible = "avic,tm070ddh03",
> .data = _tm070ddh03,
> }, {
> +   .compatible = "boe,nv101wxmn51",
> +   .data = _nv101wxmn51,
> +   }, {
> .compatible = "chunghwa,claa070wp03xg",
> .data = _claa070wp03xg,
> }, {
> --
> 2.7.4
>
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Re: [PATCH v2 2/2] drm/panel: simple: Add support BOE nv101wxmn51

2016-12-12 Thread Stéphane Marchesin
On Wed, Dec 7, 2016 at 11:26 PM, Caesar Wang  wrote:
> 10.1WXGA is a color active matrix TFT LCD module using amorphous silicon
> TFT's as an active switching devices. It can be supported by the
> simple-panel driver.
>
> Read the panel edid information;
>
> EDID MODE DETAILS
> name = 
> pixel_clock = 71900
> lvds_dual_channel = 0
> refresh = 0
> ha = 1280
> hbl = 160
> hso = 48
> hspw = 32
> hborder = 0
> va = 800
> vbl = 32
> vso = 3
> vspw = 5
> vborder = 0
> phsync = +
> pvsync = -
> x_mm = 0
> y_mm = 0
> drm_display_mode
> .hdisplay = 1280
> .hsync_start = 1328
> .hsync_end = 1360
> .htotal = 1440
> .vdisplay = 800
> .vsync_start = 803
> .vsync_end = 808
> .vtotal = 832
>
> Signed-off-by: Caesar Wang 
> ---
>
> Changes in v2:
> - fix the vsync_start and vsync_end from the edid.
> - change the commit.
>
>  drivers/gpu/drm/panel/panel-simple.c | 31 +++
>  1 file changed, 31 insertions(+)
>
> diff --git a/drivers/gpu/drm/panel/panel-simple.c 
> b/drivers/gpu/drm/panel/panel-simple.c
> index 06aaf79..7c90f16 100644
> --- a/drivers/gpu/drm/panel/panel-simple.c
> +++ b/drivers/gpu/drm/panel/panel-simple.c
> @@ -668,6 +668,34 @@ static const struct panel_desc avic_tm070ddh03 = {
> },
>  };
>
> +static const struct drm_display_mode boe_nv101wxmn51_mode = {
> +   .clock = 71900,
> +   .hdisplay = 1280,
> +   .hsync_start = 1280 + 48,
> +   .hsync_end = 1280 + 48 + 32,
> +   .htotal = 1280 + 48 + 32 + 80,
> +   .vdisplay = 800,
> +   .vsync_start = 800 + 3,
> +   .vsync_end = 800 + 3 + 5,
> +   .vtotal = 800 + 3 + 5 + 24,
> +   .vrefresh = 60,
> +};
> +
> +static const struct panel_desc boe_nv101wxmn51 = {
> +   .modes = _nv101wxmn51_mode,
> +   .num_modes = 1,

There are two modes in the EDID (there is a downclock one). Can you
add both modes?

Stéphane

> +   .bpc = 8,
> +   .size = {
> +   .width = 217,
> +   .height = 136,
> +   },
> +   .delay = {
> +   .prepare = 210,
> +   .enable = 50,
> +   .unprepare = 160,
> +   },
> +};
> +
>  static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
> .clock = 66770,
> .hdisplay = 800,
> @@ -1748,6 +1776,9 @@ static const struct of_device_id platform_of_match[] = {
> .compatible = "avic,tm070ddh03",
> .data = _tm070ddh03,
> }, {
> +   .compatible = "boe,nv101wxmn51",
> +   .data = _nv101wxmn51,
> +   }, {
> .compatible = "chunghwa,claa070wp03xg",
> .data = _claa070wp03xg,
> }, {
> --
> 2.7.4
>
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[PATCH v2 2/2] drm/panel: simple: Add support BOE nv101wxmn51

2016-12-07 Thread Caesar Wang
10.1WXGA is a color active matrix TFT LCD module using amorphous silicon
TFT's as an active switching devices. It can be supported by the
simple-panel driver.

Read the panel edid information;

EDID MODE DETAILS
name = 
pixel_clock = 71900
lvds_dual_channel = 0
refresh = 0
ha = 1280
hbl = 160
hso = 48
hspw = 32
hborder = 0
va = 800
vbl = 32
vso = 3
vspw = 5
vborder = 0
phsync = +
pvsync = -
x_mm = 0
y_mm = 0
drm_display_mode
.hdisplay = 1280
.hsync_start = 1328
.hsync_end = 1360
.htotal = 1440
.vdisplay = 800
.vsync_start = 803
.vsync_end = 808
.vtotal = 832

Signed-off-by: Caesar Wang 
---

Changes in v2:
- fix the vsync_start and vsync_end from the edid.
- change the commit.

 drivers/gpu/drm/panel/panel-simple.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-simple.c 
b/drivers/gpu/drm/panel/panel-simple.c
index 06aaf79..7c90f16 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -668,6 +668,34 @@ static const struct panel_desc avic_tm070ddh03 = {
},
 };
 
+static const struct drm_display_mode boe_nv101wxmn51_mode = {
+   .clock = 71900,
+   .hdisplay = 1280,
+   .hsync_start = 1280 + 48,
+   .hsync_end = 1280 + 48 + 32,
+   .htotal = 1280 + 48 + 32 + 80,
+   .vdisplay = 800,
+   .vsync_start = 800 + 3,
+   .vsync_end = 800 + 3 + 5,
+   .vtotal = 800 + 3 + 5 + 24,
+   .vrefresh = 60,
+};
+
+static const struct panel_desc boe_nv101wxmn51 = {
+   .modes = _nv101wxmn51_mode,
+   .num_modes = 1,
+   .bpc = 8,
+   .size = {
+   .width = 217,
+   .height = 136,
+   },
+   .delay = {
+   .prepare = 210,
+   .enable = 50,
+   .unprepare = 160,
+   },
+};
+
 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
.clock = 66770,
.hdisplay = 800,
@@ -1748,6 +1776,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "avic,tm070ddh03",
.data = _tm070ddh03,
}, {
+   .compatible = "boe,nv101wxmn51",
+   .data = _nv101wxmn51,
+   }, {
.compatible = "chunghwa,claa070wp03xg",
.data = _claa070wp03xg,
}, {
-- 
2.7.4



[PATCH v2 2/2] drm/panel: simple: Add support BOE nv101wxmn51

2016-12-07 Thread Caesar Wang
10.1WXGA is a color active matrix TFT LCD module using amorphous silicon
TFT's as an active switching devices. It can be supported by the
simple-panel driver.

Read the panel edid information;

EDID MODE DETAILS
name = 
pixel_clock = 71900
lvds_dual_channel = 0
refresh = 0
ha = 1280
hbl = 160
hso = 48
hspw = 32
hborder = 0
va = 800
vbl = 32
vso = 3
vspw = 5
vborder = 0
phsync = +
pvsync = -
x_mm = 0
y_mm = 0
drm_display_mode
.hdisplay = 1280
.hsync_start = 1328
.hsync_end = 1360
.htotal = 1440
.vdisplay = 800
.vsync_start = 803
.vsync_end = 808
.vtotal = 832

Signed-off-by: Caesar Wang 
---

Changes in v2:
- fix the vsync_start and vsync_end from the edid.
- change the commit.

 drivers/gpu/drm/panel/panel-simple.c | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/panel/panel-simple.c 
b/drivers/gpu/drm/panel/panel-simple.c
index 06aaf79..7c90f16 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -668,6 +668,34 @@ static const struct panel_desc avic_tm070ddh03 = {
},
 };
 
+static const struct drm_display_mode boe_nv101wxmn51_mode = {
+   .clock = 71900,
+   .hdisplay = 1280,
+   .hsync_start = 1280 + 48,
+   .hsync_end = 1280 + 48 + 32,
+   .htotal = 1280 + 48 + 32 + 80,
+   .vdisplay = 800,
+   .vsync_start = 800 + 3,
+   .vsync_end = 800 + 3 + 5,
+   .vtotal = 800 + 3 + 5 + 24,
+   .vrefresh = 60,
+};
+
+static const struct panel_desc boe_nv101wxmn51 = {
+   .modes = _nv101wxmn51_mode,
+   .num_modes = 1,
+   .bpc = 8,
+   .size = {
+   .width = 217,
+   .height = 136,
+   },
+   .delay = {
+   .prepare = 210,
+   .enable = 50,
+   .unprepare = 160,
+   },
+};
+
 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
.clock = 66770,
.hdisplay = 800,
@@ -1748,6 +1776,9 @@ static const struct of_device_id platform_of_match[] = {
.compatible = "avic,tm070ddh03",
.data = _tm070ddh03,
}, {
+   .compatible = "boe,nv101wxmn51",
+   .data = _nv101wxmn51,
+   }, {
.compatible = "chunghwa,claa070wp03xg",
.data = _claa070wp03xg,
}, {
-- 
2.7.4