Re: [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
Hi,
On 01.11.2013 20:58, Tomasz Figa wrote:
Hi,
On Monday 14 of October 2013 19:08:23 Vyacheslav Tyrtov wrote:
From: Tarek Dakhran
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 251
+ include/dt-bindings/clock/exynos5410.h
| 175 ++ 4 files changed, 464 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/exynos5410-clock.txt create
mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
The driver looks pretty good now, thanks for addressing my comments to
previous version. There are still few issues remaining, though. Please see
my comments inline.
[snip]
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c new file mode 100644
index 000..c5eba08
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
[snip]
+static struct of_device_id ext_clk_match[] __initdata = {
+ { .compatible = "samsung,clock-oscclk", .data = (void *)0, },
+ { },
+};
I don't see anything in binding documentation mentioning this compatible
value. Anyway, since there is already a generic binding for fixed rate
clocks, this shouldn't be needed at all.
+
+/* register exynos5410 clocks */
+static void __init exynos5410_clk_init(struct device_node *np)
+{
+ void __iomem *reg_base;
+
+ reg_base = of_iomap(np, 0);
+ if (!reg_base)
+ panic("%s: failed to map registers\n", __func__);
+
+ samsung_clk_init(np, reg_base, CLK_NR_CLKS,
+ exynos5410_clk_regs,
ARRAY_SIZE(exynos5410_clk_regs),
+ NULL, 0);
+ samsung_clk_of_register_fixed_ext(exynos5410_frt_ext_clks,
+ ARRAY_SIZE(exynos5410_frt_ext_clks),
+ ext_clk_match);
This call could be dropped after moving to generic fixed rate clock
bindings.
Best regards,
Tomasz
Already done. Will be added in patch v3.
Thank you for comments, Tomasz.
Best regards,
Tarek Dakhran
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
Hi,
On Monday 14 of October 2013 19:08:23 Vyacheslav Tyrtov wrote:
> From: Tarek Dakhran
>
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.
>
> Signed-off-by: Tarek Dakhran
> Signed-off-by: Vyacheslav Tyrtov
> ---
> .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-exynos5410.c | 251
> + include/dt-bindings/clock/exynos5410.h
> | 175 ++ 4 files changed, 464 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/exynos5410-clock.txt create
> mode 100644 drivers/clk/samsung/clk-exynos5410.c
> create mode 100644 include/dt-bindings/clock/exynos5410.h
The driver looks pretty good now, thanks for addressing my comments to
previous version. There are still few issues remaining, though. Please see
my comments inline.
[snip]
> diff --git a/drivers/clk/samsung/clk-exynos5410.c
> b/drivers/clk/samsung/clk-exynos5410.c new file mode 100644
> index 000..c5eba08
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos5410.c
[snip]
> +static struct of_device_id ext_clk_match[] __initdata = {
> + { .compatible = "samsung,clock-oscclk", .data = (void *)0, },
> + { },
> +};
I don't see anything in binding documentation mentioning this compatible
value. Anyway, since there is already a generic binding for fixed rate
clocks, this shouldn't be needed at all.
> +
> +/* register exynos5410 clocks */
> +static void __init exynos5410_clk_init(struct device_node *np)
> +{
> + void __iomem *reg_base;
> +
> + reg_base = of_iomap(np, 0);
> + if (!reg_base)
> + panic("%s: failed to map registers\n", __func__);
> +
> + samsung_clk_init(np, reg_base, CLK_NR_CLKS,
> + exynos5410_clk_regs,
ARRAY_SIZE(exynos5410_clk_regs),
> + NULL, 0);
> + samsung_clk_of_register_fixed_ext(exynos5410_frt_ext_clks,
> + ARRAY_SIZE(exynos5410_frt_ext_clks),
> + ext_clk_match);
This call could be dropped after moving to generic fixed rate clock
bindings.
Best regards,
Tomasz
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
Nevermind, didn't read the clk-pll.c properly..
pll_35xx and pl_2550 will default to the same code.
Best Regards,
Mauro
On Fri, Nov 1, 2013 at 1:53 PM, Mauro Ribeiro wrote:
> Is the PLL35xx driver compatible with the ones used on 5410?
>
> +static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
> + [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
> APLL_LOCK,
> + APLL_CON0, NULL),
> + [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll",
> CPLL_LOCK,
> + CPLL_CON0, NULL),
> + [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
> MPLL_LOCK,
> + MPLL_CON0, NULL),
> + [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
> BPLL_LOCK,
> + BPLL_CON0, NULL),
> + [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll",
> KPLL_LOCK,
> + KPLL_CON0, NULL),
>
> It registers all the PLL's with the same PLL. While the manual says
> others PLL names.
>
> Regards,
> Mauro
>
> On Tue, Oct 22, 2013 at 7:44 AM, Mike Turquette wrote:
>> Quoting Vyacheslav Tyrtov (2013-10-14 08:08:23)
>>> From: Tarek Dakhran
>>>
>>> The EXYNOS5410 clocks are statically listed and registered
>>> using the Samsung specific common clock helper functions.
>>>
>>> Signed-off-by: Tarek Dakhran
>>> Signed-off-by: Vyacheslav Tyrtov
>>
>> Looks good to me. Any objections for me to take this through the clk
>> tree?
>>
>> Regards,
>> Mike
>>
>>> ---
>>> .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
>>> drivers/clk/samsung/Makefile | 1 +
>>> drivers/clk/samsung/clk-exynos5410.c | 251
>>> +
>>> include/dt-bindings/clock/exynos5410.h | 175 ++
>>> 4 files changed, 464 insertions(+)
>>> create mode 100644
>>> Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>>> create mode 100644 drivers/clk/samsung/clk-exynos5410.c
>>> create mode 100644 include/dt-bindings/clock/exynos5410.h
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>>> b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>>> new file mode 100644
>>> index 000..a462da231
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>>> @@ -0,0 +1,37 @@
>>> +* Samsung Exynos5410 Clock Controller
>>> +
>>> +The Exynos5410 clock controller generates and supplies clock to various
>>> +controllers within the Exynos5410 SoC.
>>> +
>>> +Required Properties:
>>> +
>>> +- compatible: should be "samsung,exynos5410-clock"
>>> +
>>> +- reg: physical base address of the controller and length of memory mapped
>>> + region.
>>> +
>>> +- #clock-cells: should be 1.
>>> +
>>> +All available clocks are defined as preprocessor macros in
>>> +dt-bindings/clock/exynos5410.h header and can be used in device
>>> +tree sources.
>>> +
>>> +Example 1: An example of a clock controller node is listed below.
>>> +
>>> + clock: clock-controller@0x1001 {
>>> + compatible = "samsung,exynos5410-clock";
>>> + reg = <0x1001 0x3>;
>>> + #clock-cells = <1>;
>>> + };
>>> +
>>> +Example 2: UART controller node that consumes the clock generated by the
>>> clock
>>> + controller. Refer to the standard clock bindings for information
>>> + about 'clocks' and 'clock-names' property.
>>> +
>>> + serial@12C2 {
>>> + compatible = "samsung,exynos4210-uart";
>>> + reg = <0x12C0 0x100>;
>>> + interrupts = <0 51 0>;
>>> + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
>>> + clock-names = "uart", "clk_uart_baud0";
>>> + };
>>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>>> index 3413380..5a446ca 100644
>>> --- a/drivers/clk/samsung/Makefile
>>> +++ b/drivers/clk/samsung/Makefile
>>> @@ -5,6 +5,7 @@
>>> obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
>>> obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
>>> obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
>>> +obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
>>> obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
>>> obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
>>> obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
>>> diff --git a/drivers/clk/samsung/clk-exynos5410.c
>>> b/drivers/clk/samsung/clk-exynos5410.c
>>> new file mode 100644
>>> index 000..c5eba08
>>> --- /dev/null
>>> +++ b/drivers/clk/samsung/clk-exynos5410.c
>>> @@ -0,0 +1,251 @@
>>> +/*
>>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>>> + * Author: Tarek Dakhran
>>> + *
>>> + * This program is free software; you can redistribute it and/or modify
>>> + * it under the terms of the GNU General Public License version 2 as
>>> + * published by the Free Software Foundation.
>>> + *
>>> + * Common Clock Framework support for Exynos5410 SoC.
>
Re: [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
Is the PLL35xx driver compatible with the ones used on 5410?
+static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
+ [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
+ APLL_CON0, NULL),
+ [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
+ CPLL_CON0, NULL),
+ [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
+ MPLL_CON0, NULL),
+ [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
+ BPLL_CON0, NULL),
+ [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
+ KPLL_CON0, NULL),
It registers all the PLL's with the same PLL. While the manual says
others PLL names.
Regards,
Mauro
On Tue, Oct 22, 2013 at 7:44 AM, Mike Turquette wrote:
> Quoting Vyacheslav Tyrtov (2013-10-14 08:08:23)
>> From: Tarek Dakhran
>>
>> The EXYNOS5410 clocks are statically listed and registered
>> using the Samsung specific common clock helper functions.
>>
>> Signed-off-by: Tarek Dakhran
>> Signed-off-by: Vyacheslav Tyrtov
>
> Looks good to me. Any objections for me to take this through the clk
> tree?
>
> Regards,
> Mike
>
>> ---
>> .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
>> drivers/clk/samsung/Makefile | 1 +
>> drivers/clk/samsung/clk-exynos5410.c | 251
>> +
>> include/dt-bindings/clock/exynos5410.h | 175 ++
>> 4 files changed, 464 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> create mode 100644 drivers/clk/samsung/clk-exynos5410.c
>> create mode 100644 include/dt-bindings/clock/exynos5410.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> new file mode 100644
>> index 000..a462da231
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
>> @@ -0,0 +1,37 @@
>> +* Samsung Exynos5410 Clock Controller
>> +
>> +The Exynos5410 clock controller generates and supplies clock to various
>> +controllers within the Exynos5410 SoC.
>> +
>> +Required Properties:
>> +
>> +- compatible: should be "samsung,exynos5410-clock"
>> +
>> +- reg: physical base address of the controller and length of memory mapped
>> + region.
>> +
>> +- #clock-cells: should be 1.
>> +
>> +All available clocks are defined as preprocessor macros in
>> +dt-bindings/clock/exynos5410.h header and can be used in device
>> +tree sources.
>> +
>> +Example 1: An example of a clock controller node is listed below.
>> +
>> + clock: clock-controller@0x1001 {
>> + compatible = "samsung,exynos5410-clock";
>> + reg = <0x1001 0x3>;
>> + #clock-cells = <1>;
>> + };
>> +
>> +Example 2: UART controller node that consumes the clock generated by the
>> clock
>> + controller. Refer to the standard clock bindings for information
>> + about 'clocks' and 'clock-names' property.
>> +
>> + serial@12C2 {
>> + compatible = "samsung,exynos4210-uart";
>> + reg = <0x12C0 0x100>;
>> + interrupts = <0 51 0>;
>> + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
>> + clock-names = "uart", "clk_uart_baud0";
>> + };
>> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
>> index 3413380..5a446ca 100644
>> --- a/drivers/clk/samsung/Makefile
>> +++ b/drivers/clk/samsung/Makefile
>> @@ -5,6 +5,7 @@
>> obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
>> obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
>> obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
>> +obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
>> obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
>> obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
>> obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
>> diff --git a/drivers/clk/samsung/clk-exynos5410.c
>> b/drivers/clk/samsung/clk-exynos5410.c
>> new file mode 100644
>> index 000..c5eba08
>> --- /dev/null
>> +++ b/drivers/clk/samsung/clk-exynos5410.c
>> @@ -0,0 +1,251 @@
>> +/*
>> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
>> + * Author: Tarek Dakhran
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * Common Clock Framework support for Exynos5410 SoC.
>> +*/
>> +
>> +#include
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "clk.h"
>> +
>> +#define APLL_LOCK 0x0
>> +#define APLL_CON0 0x100
>> +#define CPLL_LOCK 0x10020
>> +#define CPLL_CON0 0x10120
>> +#define MPLL_LOCK
Re: [PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
Quoting Vyacheslav Tyrtov (2013-10-14 08:08:23)
> From: Tarek Dakhran
>
> The EXYNOS5410 clocks are statically listed and registered
> using the Samsung specific common clock helper functions.
>
> Signed-off-by: Tarek Dakhran
> Signed-off-by: Vyacheslav Tyrtov
Looks good to me. Any objections for me to take this through the clk
tree?
Regards,
Mike
> ---
> .../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
> drivers/clk/samsung/Makefile | 1 +
> drivers/clk/samsung/clk-exynos5410.c | 251
> +
> include/dt-bindings/clock/exynos5410.h | 175 ++
> 4 files changed, 464 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> create mode 100644 drivers/clk/samsung/clk-exynos5410.c
> create mode 100644 include/dt-bindings/clock/exynos5410.h
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> new file mode 100644
> index 000..a462da231
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
> @@ -0,0 +1,37 @@
> +* Samsung Exynos5410 Clock Controller
> +
> +The Exynos5410 clock controller generates and supplies clock to various
> +controllers within the Exynos5410 SoC.
> +
> +Required Properties:
> +
> +- compatible: should be "samsung,exynos5410-clock"
> +
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +
> +- #clock-cells: should be 1.
> +
> +All available clocks are defined as preprocessor macros in
> +dt-bindings/clock/exynos5410.h header and can be used in device
> +tree sources.
> +
> +Example 1: An example of a clock controller node is listed below.
> +
> + clock: clock-controller@0x1001 {
> + compatible = "samsung,exynos5410-clock";
> + reg = <0x1001 0x3>;
> + #clock-cells = <1>;
> + };
> +
> +Example 2: UART controller node that consumes the clock generated by the
> clock
> + controller. Refer to the standard clock bindings for information
> + about 'clocks' and 'clock-names' property.
> +
> + serial@12C2 {
> + compatible = "samsung,exynos4210-uart";
> + reg = <0x12C0 0x100>;
> + interrupts = <0 51 0>;
> + clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
> + clock-names = "uart", "clk_uart_baud0";
> + };
> diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
> index 3413380..5a446ca 100644
> --- a/drivers/clk/samsung/Makefile
> +++ b/drivers/clk/samsung/Makefile
> @@ -5,6 +5,7 @@
> obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
> obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
> obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
> +obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
> obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
> obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
> obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
> diff --git a/drivers/clk/samsung/clk-exynos5410.c
> b/drivers/clk/samsung/clk-exynos5410.c
> new file mode 100644
> index 000..c5eba08
> --- /dev/null
> +++ b/drivers/clk/samsung/clk-exynos5410.c
> @@ -0,0 +1,251 @@
> +/*
> + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
> + * Author: Tarek Dakhran
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * Common Clock Framework support for Exynos5410 SoC.
> +*/
> +
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "clk.h"
> +
> +#define APLL_LOCK 0x0
> +#define APLL_CON0 0x100
> +#define CPLL_LOCK 0x10020
> +#define CPLL_CON0 0x10120
> +#define MPLL_LOCK 0x4000
> +#define MPLL_CON0 0x4100
> +#define BPLL_LOCK 0x20010
> +#define BPLL_CON0 0x20110
> +#define KPLL_LOCK 0x28000
> +#define KPLL_CON0 0x28100
> +
> +#define SRC_CPU0x200
> +#define DIV_CPU0 0x500
> +#define SRC_CPERI1 0x4204
> +#define DIV_TOP0 0x10510
> +#define DIV_TOP1 0x10514
> +#define DIV_FSYS1 0x1054c
> +#define DIV_FSYS2 0x10550
> +#define DIV_PERIC0 0x10558
> +#define SRC_TOP0 0x10210
> +#define SRC_TOP1 0x10214
> +#define SRC_TOP2 0x10218
> +#define SRC_FSYS 0x10244
> +#define SRC_PERIC0 0x10250
> +#define SRC_MASK_FSYS 0x10340
> +#define SRC_MASK_PERIC00x10350
> +#define GATE_BUS_FSYS0 0x10740
> +#define GATE_IP_FSYS 0x10944
> +#define GATE_IP_PERIC
[PATCH v2 2/4] clk: exynos5410: register clocks using common clock framework
From: Tarek Dakhran
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Signed-off-by: Vyacheslav Tyrtov
---
.../devicetree/bindings/clock/exynos5410-clock.txt | 37 +++
drivers/clk/samsung/Makefile | 1 +
drivers/clk/samsung/clk-exynos5410.c | 251 +
include/dt-bindings/clock/exynos5410.h | 175 ++
4 files changed, 464 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/exynos5410-clock.txt
create mode 100644 drivers/clk/samsung/clk-exynos5410.c
create mode 100644 include/dt-bindings/clock/exynos5410.h
diff --git a/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
new file mode 100644
index 000..a462da231
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos5410-clock.txt
@@ -0,0 +1,37 @@
+* Samsung Exynos5410 Clock Controller
+
+The Exynos5410 clock controller generates and supplies clock to various
+controllers within the Exynos5410 SoC.
+
+Required Properties:
+
+- compatible: should be "samsung,exynos5410-clock"
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+
+- #clock-cells: should be 1.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos5410.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+ clock: clock-controller@0x1001 {
+ compatible = "samsung,exynos5410-clock";
+ reg = <0x1001 0x3>;
+ #clock-cells = <1>;
+ };
+
+Example 2: UART controller node that consumes the clock generated by the clock
+ controller. Refer to the standard clock bindings for information
+ about 'clocks' and 'clock-names' property.
+
+ serial@12C2 {
+ compatible = "samsung,exynos4210-uart";
+ reg = <0x12C0 0x100>;
+ interrupts = <0 51 0>;
+ clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+ clock-names = "uart", "clk_uart_baud0";
+ };
diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile
index 3413380..5a446ca 100644
--- a/drivers/clk/samsung/Makefile
+++ b/drivers/clk/samsung/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_COMMON_CLK) += clk.o clk-pll.o
obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
+obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-exynos5410.c
new file mode 100644
index 000..c5eba08
--- /dev/null
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * Author: Tarek Dakhran
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Common Clock Framework support for Exynos5410 SoC.
+*/
+
+#include
+
+#include
+#include
+#include
+#include
+#include
+
+#include "clk.h"
+
+#define APLL_LOCK 0x0
+#define APLL_CON0 0x100
+#define CPLL_LOCK 0x10020
+#define CPLL_CON0 0x10120
+#define MPLL_LOCK 0x4000
+#define MPLL_CON0 0x4100
+#define BPLL_LOCK 0x20010
+#define BPLL_CON0 0x20110
+#define KPLL_LOCK 0x28000
+#define KPLL_CON0 0x28100
+
+#define SRC_CPU0x200
+#define DIV_CPU0 0x500
+#define SRC_CPERI1 0x4204
+#define DIV_TOP0 0x10510
+#define DIV_TOP1 0x10514
+#define DIV_FSYS1 0x1054c
+#define DIV_FSYS2 0x10550
+#define DIV_PERIC0 0x10558
+#define SRC_TOP0 0x10210
+#define SRC_TOP1 0x10214
+#define SRC_TOP2 0x10218
+#define SRC_FSYS 0x10244
+#define SRC_PERIC0 0x10250
+#define SRC_MASK_FSYS 0x10340
+#define SRC_MASK_PERIC00x10350
+#define GATE_BUS_FSYS0 0x10740
+#define GATE_IP_FSYS 0x10944
+#define GATE_IP_PERIC 0x10950
+#define GATE_IP_PERIS 0x10960
+#define SRC_CDREX 0x20200
+#define SRC_KFC0x28200
+#define DIV_KFC0 0x28500
+
+/* list of PLLs */
+enum exynos5410_plls {
+ apll, cpll, mpll,
+ bpll, kpll,
+ nr_plls /* number of PLLs */
+};
+
+/*
+ * list of controller registers to be saved and restored during a
+ * suspe
