[PATCH v2 3/3] ARM: STi: Add STiH416 ethernet support.
From: Srinivas Kandagatla
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla
---
arch/arm/boot/dts/stih416-clock.dtsi | 14
arch/arm/boot/dts/stih416-pinctrl.dtsi | 109
arch/arm/boot/dts/stih416.dtsi | 44 +
3 files changed, 167 insertions(+)
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi
b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1..a6942c7 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
clock-frequency = <1>;
clock-output-names = "CLK_S_ICN_REG_0";
};
+
+ CLK_S_GMAC0_PHY: clockgenA1@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ clock-output-names = "CLK_S_GMAC0_PHY";
+ };
+
+ CLK_S_ETH1_PHY: clockgenA0@7 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <2500>;
+ clock-output-names = "CLK_S_ETH1_PHY";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi
b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 8863c38..c4beef2 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -132,6 +132,58 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = < 0 ALT1 OUT
SE_NICLK_IO 0 CLK_A>;
+ txd1 = < 1 ALT1 OUT
SE_NICLK_IO 0 CLK_A>;
+ txd2 = < 2 ALT1 OUT
SE_NICLK_IO 0 CLK_A>;
+ txd3 = < 3 ALT1 OUT
SE_NICLK_IO 0 CLK_A>;
+ txer = < 4 ALT1 OUT
SE_NICLK_IO 0 CLK_A>;
+ txen = < 5 ALT1 OUT
SE_NICLK_IO 0 CLK_A>;
+ txclk = < 6 ALT1 IN NICLK
0 CLK_A>;
+ col = < 7 ALT1 IN BYPASS
1000>;
+
+ mdio = < 0 ALT1 OUT
BYPASS 1500>;
+ mdc = < 1 ALT1 OUT NICLK
0 CLK_A>;
+ crs = < 2 ALT1 IN BYPASS
1000>;
+ mdint = < 3 ALT1 IN BYPASS
0>;
+ rxd0 = < 4 ALT1 IN
SE_NICLK_IO 0 CLK_A>;
+ rxd1 = < 5 ALT1 IN
SE_NICLK_IO 0 CLK_A>;
+ rxd2 = < 6 ALT1 IN
SE_NICLK_IO 0 CLK_A>;
+ rxd3 = < 7 ALT1 IN
SE_NICLK_IO 0 CLK_A>;
+
+ rxdv = < 0 ALT1 IN
SE_NICLK_IO 0 CLK_A>;
+ rx_er = < 1 ALT1 IN
SE_NICLK_IO 0 CLK_A>;
+ rxclk = < 2 ALT1 IN NICLK
0 CLK_A>;
+ phyclk = < 3 ALT1 OUT
NICLK 0 CLK_A>;
+ };
+ };
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = < 0 ALT1 OUT DE_IO
500 CLK_A>;
+ txd1 = < 1 ALT1 OUT DE_IO
500 CLK_A>;
+ txd2 = < 2 ALT1 OUT DE_IO
500 CLK_A>;
+ txd3 = < 3 ALT1 OUT DE_IO
500 CLK_A>;
+ txen = < 5 ALT1 OUT DE_IO
0 CLK_A>;
+ txclk = < 6 ALT1 IN NICLK
0 CLK_A>;
+
+ mdio = < 0 ALT1 OUT BYPASS
0>;
+ mdc = < 1 ALT1 OUT NICLK
0 CLK_A>;
+ rxd0 = < 4 ALT1 IN DE_IO
500 CLK_A>;
+ rxd1 = < 5 ALT1 IN DE_IO
500 CLK_A>;
+ rxd2 = < 6 ALT1 IN DE_IO
500 CLK_A>;
+ rxd3 = < 7 ALT1 IN DE_IO
500 CLK_A>;
+
+ rxdv = < 0
[PATCH v2 3/3] ARM: STi: Add STiH416 ethernet support.
From: Srinivas Kandagatla srinivas.kandaga...@st.com
This patch adds support to STiH416 SOC, which has two ethernet
snps,dwmac controllers version 3.710. With this patch B2000 and B2020
boards can boot with ethernet in MII and RGMII modes.
Tested on both B2020 and B2000.
Signed-off-by: Srinivas Kandagatla srinivas.kandaga...@st.com
---
arch/arm/boot/dts/stih416-clock.dtsi | 14
arch/arm/boot/dts/stih416-pinctrl.dtsi | 109
arch/arm/boot/dts/stih416.dtsi | 44 +
3 files changed, 167 insertions(+)
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi
b/arch/arm/boot/dts/stih416-clock.dtsi
index 7026bf1..a6942c7 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -37,5 +37,19 @@
clock-frequency = 1;
clock-output-names = CLK_S_ICN_REG_0;
};
+
+ CLK_S_GMAC0_PHY: clockgenA1@7 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2500;
+ clock-output-names = CLK_S_GMAC0_PHY;
+ };
+
+ CLK_S_ETH1_PHY: clockgenA0@7 {
+ #clock-cells = 0;
+ compatible = fixed-clock;
+ clock-frequency = 2500;
+ clock-output-names = CLK_S_ETH1_PHY;
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi
b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index 8863c38..c4beef2 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -132,6 +132,58 @@
};
};
};
+
+ gmac1 {
+ pinctrl_mii1: mii1 {
+ st,pins {
+ txd0 = PIO0 0 ALT1 OUT
SE_NICLK_IO 0 CLK_A;
+ txd1 = PIO0 1 ALT1 OUT
SE_NICLK_IO 0 CLK_A;
+ txd2 = PIO0 2 ALT1 OUT
SE_NICLK_IO 0 CLK_A;
+ txd3 = PIO0 3 ALT1 OUT
SE_NICLK_IO 0 CLK_A;
+ txer = PIO0 4 ALT1 OUT
SE_NICLK_IO 0 CLK_A;
+ txen = PIO0 5 ALT1 OUT
SE_NICLK_IO 0 CLK_A;
+ txclk = PIO0 6 ALT1 IN NICLK
0 CLK_A;
+ col = PIO0 7 ALT1 IN BYPASS
1000;
+
+ mdio = PIO1 0 ALT1 OUT
BYPASS 1500;
+ mdc = PIO1 1 ALT1 OUT NICLK
0 CLK_A;
+ crs = PIO1 2 ALT1 IN BYPASS
1000;
+ mdint = PIO1 3 ALT1 IN BYPASS
0;
+ rxd0 = PIO1 4 ALT1 IN
SE_NICLK_IO 0 CLK_A;
+ rxd1 = PIO1 5 ALT1 IN
SE_NICLK_IO 0 CLK_A;
+ rxd2 = PIO1 6 ALT1 IN
SE_NICLK_IO 0 CLK_A;
+ rxd3 = PIO1 7 ALT1 IN
SE_NICLK_IO 0 CLK_A;
+
+ rxdv = PIO2 0 ALT1 IN
SE_NICLK_IO 0 CLK_A;
+ rx_er = PIO2 1 ALT1 IN
SE_NICLK_IO 0 CLK_A;
+ rxclk = PIO2 2 ALT1 IN NICLK
0 CLK_A;
+ phyclk = PIO2 3 ALT1 OUT
NICLK 0 CLK_A;
+ };
+ };
+ pinctrl_rgmii1: rgmii1-0 {
+ st,pins {
+ txd0 = PIO0 0 ALT1 OUT DE_IO
500 CLK_A;
+ txd1 = PIO0 1 ALT1 OUT DE_IO
500 CLK_A;
+ txd2 = PIO0 2 ALT1 OUT DE_IO
500 CLK_A;
+ txd3 = PIO0 3 ALT1 OUT DE_IO
500 CLK_A;
+ txen = PIO0 5 ALT1 OUT DE_IO
0 CLK_A;
+ txclk = PIO0 6 ALT1 IN NICLK
0 CLK_A;
+
+ mdio = PIO1 0 ALT1 OUT BYPASS
0;
+ mdc = PIO1 1 ALT1 OUT NICLK
0 CLK_A;
+ rxd0 = PIO1 4 ALT1 IN DE_IO
500 CLK_A;
+ rxd1 = PIO1 5 ALT1 IN DE_IO
500 CLK_A;
+ rxd2 = PIO1 6 ALT1 IN DE_IO
500 CLK_A;
+ rxd3 =
