Re: [PATCH v2 3/4] clk: Add Baikal-T1 CCU PLLs driver
On Wed, May 06, 2020 at 03:27:57PM -0700, Randy Dunlap wrote: > Hi, > > Typo(s): > > On 5/6/20 3:22 PM, Serge Semin wrote: > > diff --git a/drivers/clk/baikal-t1/Kconfig b/drivers/clk/baikal-t1/Kconfig > > new file mode 100644 > > index ..e1257af9f49e > > --- /dev/null > > +++ b/drivers/clk/baikal-t1/Kconfig > > @@ -0,0 +1,30 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +config CLK_BAIKAL_T1 > > + bool "Baikal-T1 Clocks Control Unit interface" > > + depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST > > + default MIPS_BAIKAL_T1 > > + help > > + Clocks Control Unit is the core of Baikal-T1 SoC System Controller > > + responsible for the chip subsystems clocking and resetting. It > > + consists of multiple global clock domains, which can be reset by > > + means of the CCU control registers. These domains and devices placed > > + in them are fed with clocks generated by a hierarchy of PLLs, > > + configurable and fixed clock dividers. Enable this option to be able > > + to select Baikal-T1 CCU PLLs and Dividers drivers. > > + > > +if CLK_BAIKAL_T1 > > + > > +config CLK_BT1_CCU_PLL > > + bool "Baikal-T1 CCU PLLs support" > > + select MFD_SYSCON > > + default MIPS_BAIKAL_T1 > > + help > > + Enable this to support the PLLs embedded into the Baikal-T1 SoC > > + System Controller. These are five PLLs placed at the root of the > > + clocks hierarchy, right after an external reference osciallator > > oscillator > > > + (normally of 25MHz). They are used to generate high frequency > > + signals, which are either directly wired to the consumers (like > > + CPUs, DDR, etc) or passed over the clock dividers to be only then > > and while you are here: > > etc.) Both will be fixed in v3. Thanks. -Sergey > > > + used as an individual reference clock of a target device. > > + > > +endif > > thanks. > -- > ~Randy >
Re: [PATCH v2 3/4] clk: Add Baikal-T1 CCU PLLs driver
Hello, On Wed, May 06, 2020 at 03:27:57PM -0700, Randy Dunlap wrote: > Hi, > > Typo(s): > > On 5/6/20 3:22 PM, Serge Semin wrote: > > diff --git a/drivers/clk/baikal-t1/Kconfig b/drivers/clk/baikal-t1/Kconfig > > new file mode 100644 > > index ..e1257af9f49e > > --- /dev/null > > +++ b/drivers/clk/baikal-t1/Kconfig > > @@ -0,0 +1,30 @@ > > +# SPDX-License-Identifier: GPL-2.0-only > > +config CLK_BAIKAL_T1 > > + bool "Baikal-T1 Clocks Control Unit interface" > > + depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST > > + default MIPS_BAIKAL_T1 > > + help > > + Clocks Control Unit is the core of Baikal-T1 SoC System Controller > > + responsible for the chip subsystems clocking and resetting. It > > + consists of multiple global clock domains, which can be reset by > > + means of the CCU control registers. These domains and devices placed > > + in them are fed with clocks generated by a hierarchy of PLLs, > > + configurable and fixed clock dividers. Enable this option to be able > > + to select Baikal-T1 CCU PLLs and Dividers drivers. > > + > > +if CLK_BAIKAL_T1 > > + > > +config CLK_BT1_CCU_PLL > > + bool "Baikal-T1 CCU PLLs support" > > + select MFD_SYSCON > > + default MIPS_BAIKAL_T1 > > + help > > + Enable this to support the PLLs embedded into the Baikal-T1 SoC > > + System Controller. These are five PLLs placed at the root of the > > + clocks hierarchy, right after an external reference osciallator > > oscillator Fixed. Thanks. > > > + (normally of 25MHz). They are used to generate high frequency > > + signals, which are either directly wired to the consumers (like > > + CPUs, DDR, etc) or passed over the clock dividers to be only then > > and while you are here: > > etc.) Thanks again. -Sergey > > > + used as an individual reference clock of a target device. > > + > > +endif > > thanks. > -- > ~Randy >
Re: [PATCH v2 3/4] clk: Add Baikal-T1 CCU PLLs driver
Hi, Typo(s): On 5/6/20 3:22 PM, Serge Semin wrote: > diff --git a/drivers/clk/baikal-t1/Kconfig b/drivers/clk/baikal-t1/Kconfig > new file mode 100644 > index ..e1257af9f49e > --- /dev/null > +++ b/drivers/clk/baikal-t1/Kconfig > @@ -0,0 +1,30 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +config CLK_BAIKAL_T1 > + bool "Baikal-T1 Clocks Control Unit interface" > + depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST > + default MIPS_BAIKAL_T1 > + help > + Clocks Control Unit is the core of Baikal-T1 SoC System Controller > + responsible for the chip subsystems clocking and resetting. It > + consists of multiple global clock domains, which can be reset by > + means of the CCU control registers. These domains and devices placed > + in them are fed with clocks generated by a hierarchy of PLLs, > + configurable and fixed clock dividers. Enable this option to be able > + to select Baikal-T1 CCU PLLs and Dividers drivers. > + > +if CLK_BAIKAL_T1 > + > +config CLK_BT1_CCU_PLL > + bool "Baikal-T1 CCU PLLs support" > + select MFD_SYSCON > + default MIPS_BAIKAL_T1 > + help > + Enable this to support the PLLs embedded into the Baikal-T1 SoC > + System Controller. These are five PLLs placed at the root of the > + clocks hierarchy, right after an external reference osciallator oscillator > + (normally of 25MHz). They are used to generate high frequency > + signals, which are either directly wired to the consumers (like > + CPUs, DDR, etc) or passed over the clock dividers to be only then and while you are here: etc.) > + used as an individual reference clock of a target device. > + > +endif thanks. -- ~Randy
[PATCH v2 3/4] clk: Add Baikal-T1 CCU PLLs driver
Baikal-T1 is supposed to be supplied with a high-frequency external
oscillator. But in order to create signals suitable for each IP-block
embedded into the SoC the oscillator output is primarily connected to
a set of CCU PLLs. There are five of them to create clocks for the MIPS
P5600 cores, an embedded DDR controller, SATA, Ethernet and PCIe domains.
The last three domains though named by the biggest system interfaces in
fact include nearly all of the rest SoC peripherals. Each of the PLLs is
based on True Circuits TSMC CLN28HPM IP-core with an interface wrapper
(so called safe PLL' clocks switcher) to simplify the PLL configuration
procedure.
This driver creates the of-based hardware clocks to use them then in
the corresponding subsystems. In order to simplify the driver code we
split the functionality up into the PLLs clocks operations and hardware
clocks declaration/registration procedures.
Even though the PLLs are based on the same IP-core, they may have some
differences. In particular, some CCU PLLs support the output clock change
without gating them (like CPU or PCIe PLLs), while the others don't, some
CCU PLLs are critical and aren't supposed to be gated. In order to cover
all of these cases the hardware clocks driver is designed with an
info-descriptor pattern. So there are special static descriptors declared
for each PLL, which is then used to create a hardware clock with proper
operations. Additionally debugfs-files are provided for each PLL' field
to make sure the implemented rate-PLLs-dividers calculation algorithm is
correct.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Paul Burton
Cc: Ralf Baechle
Cc: Arnd Bergmann
Cc: Rob Herring
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
Changelog v2:
- Rearrange the SoBs.
- Don't enable the CCU clock drivers by default for COMPILE_TEST config.
- Make sure the CCU drivers depend on OF kernel config only when built for
Baikal-T1-based platform.
- Fix spelling in the CCU PLL kernel config description.
- Replace lock delay and frequency calculation macro with inline functions.
- Use 64-bits arithmetics in the PLL output frequency calculation method.
- Use readl_poll_timeout_atomic() to poll the PLL lock state.
- Use FIELD_{GET,PREP}() macro instead of handwritten field setters and
getters.
- Discard CLK_IGNORE_UNUSED flag setting. It's redundant since CLK_IS_CRITICAL
is enough for cases when it's appropriate.
- Don't declare private copies of the Common Clock Flags.
- Comment out the CLK_IS_CRITICAL flag settings.
- Discard !pll test in ccu_pll_hw_unregister() method.
- Discard ccu_pll_get_clk_id() method. Use not-null check instead of FFs-
based invalid ID value.
- Discard alive probe message.
- Remove "clock-output-names" property support.
- Convert the driver to using syscon regmap instead of direct IO methods,
since now the PLLs DT node is supposed to be a sub-node of the Baikal-T1
System Controller node.
- Add DebugFS nodes in RO-mode by default.
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile| 1 +
drivers/clk/baikal-t1/Kconfig | 30 ++
drivers/clk/baikal-t1/Makefile | 2 +
drivers/clk/baikal-t1/ccu-pll.c | 558
drivers/clk/baikal-t1/ccu-pll.h | 64
drivers/clk/baikal-t1/clk-ccu-pll.c | 204 ++
7 files changed, 860 insertions(+)
create mode 100644 drivers/clk/baikal-t1/Kconfig
create mode 100644 drivers/clk/baikal-t1/Makefile
create mode 100644 drivers/clk/baikal-t1/ccu-pll.c
create mode 100644 drivers/clk/baikal-t1/ccu-pll.h
create mode 100644 drivers/clk/baikal-t1/clk-ccu-pll.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index bcb257baed06..b32da34ebcf9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -341,6 +341,7 @@ config COMMON_CLK_FIXED_MMIO
source "drivers/clk/actions/Kconfig"
source "drivers/clk/analogbits/Kconfig"
+source "drivers/clk/baikal-t1/Kconfig"
source "drivers/clk/bcm/Kconfig"
source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/imgtec/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f4169cc2fd31..1496045d4e01 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -75,6 +75,7 @@ obj-y += analogbits/
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_ARTPEC) += axis/
obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
+obj-$(CONFIG_CLK_BAIKAL_T1)+= baikal-t1/
obj-y += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
diff --git a/drivers/clk/baikal-t1/Kconfig b/drivers/clk/baikal-t1/Kconfig
new file mode 100644
index ..e1257af9f49e
--- /dev/null
+++ b/drivers/clk/baikal-t1/Kconfig
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config CLK_BAIKAL_T1
+ bool "Baikal-T1 Clocks Control Unit interfa
