[PATCH v2 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
Previously dbi accessors can be used to access data of size 4 bytes. But there might be situations (like accessing MSI_MESSAGE_CONTROL in order to set/get the number of required MSI interrupts in EP mode) where dbi accessors must be used to access data of size 2. This is in preparation for adding endpoint mode support to designware driver. Cc: Jingoo HanCc: Richard Zhu Cc: Lucas Stach Cc: Murali Karicheri Cc: Thomas Petazzoni Cc: Niklas Cassel Cc: Jesper Nilsson Cc: Joao Pinto Cc: Zhou Wang Cc: Gabriele Paoloni Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/Kconfig| 18 drivers/pci/dwc/pci-dra7xx.c |8 ++-- drivers/pci/dwc/pci-exynos.c | 16 +++ drivers/pci/dwc/pci-imx6.c | 54 +++--- drivers/pci/dwc/pci-keystone-dw.c | 13 +++--- drivers/pci/dwc/pcie-armada8k.c| 38 drivers/pci/dwc/pcie-artpec6.c |6 +-- drivers/pci/dwc/pcie-designware-host.c | 18 drivers/pci/dwc/pcie-designware.c | 77 +++- drivers/pci/dwc/pcie-designware.h | 14 +++--- drivers/pci/dwc/pcie-hisi.c| 14 +++--- 11 files changed, 147 insertions(+), 129 deletions(-) diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index dfb8a69..cb3d5d0 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -36,7 +36,7 @@ config PCIE_DW_PLAT config PCI_EXYNOS bool "Samsung Exynos PCIe controller" depends on PCI - depends on SOC_EXYNOS5440 + depends on SOC_EXYNOS5440 || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -44,7 +44,7 @@ config PCI_EXYNOS config PCI_IMX6 bool "Freescale i.MX6 PCIe controller" depends on PCI - depends on SOC_IMX6Q + depends on SOC_IMX6Q || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -52,7 +52,7 @@ config PCI_IMX6 config PCIE_SPEAR13XX bool "STMicroelectronics SPEAr PCIe controller" depends on PCI - depends on ARCH_SPEAR13XX + depends on ARCH_SPEAR13XX || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -62,7 +62,7 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" depends on PCI - depends on ARCH_KEYSTONE + depends on ARCH_KEYSTONE || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -75,7 +75,7 @@ config PCI_KEYSTONE config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" depends on PCI - depends on OF && (ARM || ARCH_LAYERSCAPE) + depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select MFD_SYSCON select PCIE_DW_HOST @@ -83,7 +83,7 @@ config PCI_LAYERSCAPE Say Y here if you want PCIe controller support on Layerscape SoCs. config PCI_HISI - depends on OF && ARM64 + depends on OF && (ARM64 || COMPILE_TEST) bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers" depends on PCI depends on PCI_MSI_IRQ_DOMAIN @@ -96,7 +96,7 @@ config PCI_HISI config PCIE_QCOM bool "Qualcomm PCIe controller" depends on PCI - depends on ARCH_QCOM && OF + depends on (ARCH_QCOM || COMPILE_TEST) && OF depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -108,7 +108,7 @@ config PCIE_QCOM config PCIE_ARMADA_8K bool "Marvell Armada-8K PCIe controller" depends on PCI - depends on ARCH_MVEBU + depends on ARCH_MVEBU || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -121,7 +121,7 @@ config PCIE_ARMADA_8K config PCIE_ARTPEC6 bool "Axis ARTPEC-6 PCIe controller" depends on PCI - depends on MACH_ARTPEC6 + depends on MACH_ARTPEC6 || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 3708bd6..c6fef0a 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -499,9 +499,9 @@ static int dra7xx_pcie_suspend(struct device *dev) u32 val; /* clear MSE */ - val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND); + val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4); val &= ~PCI_COMMAND_MEMORY; - dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val); +
[PATCH v2 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
Previously dbi accessors can be used to access data of size 4 bytes. But there might be situations (like accessing MSI_MESSAGE_CONTROL in order to set/get the number of required MSI interrupts in EP mode) where dbi accessors must be used to access data of size 2. This is in preparation for adding endpoint mode support to designware driver. Cc: Jingoo Han Cc: Richard Zhu Cc: Lucas Stach Cc: Murali Karicheri Cc: Thomas Petazzoni Cc: Niklas Cassel Cc: Jesper Nilsson Cc: Joao Pinto Cc: Zhou Wang Cc: Gabriele Paoloni Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/Kconfig| 18 drivers/pci/dwc/pci-dra7xx.c |8 ++-- drivers/pci/dwc/pci-exynos.c | 16 +++ drivers/pci/dwc/pci-imx6.c | 54 +++--- drivers/pci/dwc/pci-keystone-dw.c | 13 +++--- drivers/pci/dwc/pcie-armada8k.c| 38 drivers/pci/dwc/pcie-artpec6.c |6 +-- drivers/pci/dwc/pcie-designware-host.c | 18 drivers/pci/dwc/pcie-designware.c | 77 +++- drivers/pci/dwc/pcie-designware.h | 14 +++--- drivers/pci/dwc/pcie-hisi.c| 14 +++--- 11 files changed, 147 insertions(+), 129 deletions(-) diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig index dfb8a69..cb3d5d0 100644 --- a/drivers/pci/dwc/Kconfig +++ b/drivers/pci/dwc/Kconfig @@ -36,7 +36,7 @@ config PCIE_DW_PLAT config PCI_EXYNOS bool "Samsung Exynos PCIe controller" depends on PCI - depends on SOC_EXYNOS5440 + depends on SOC_EXYNOS5440 || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -44,7 +44,7 @@ config PCI_EXYNOS config PCI_IMX6 bool "Freescale i.MX6 PCIe controller" depends on PCI - depends on SOC_IMX6Q + depends on SOC_IMX6Q || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -52,7 +52,7 @@ config PCI_IMX6 config PCIE_SPEAR13XX bool "STMicroelectronics SPEAr PCIe controller" depends on PCI - depends on ARCH_SPEAR13XX + depends on ARCH_SPEAR13XX || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -62,7 +62,7 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" depends on PCI - depends on ARCH_KEYSTONE + depends on ARCH_KEYSTONE || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -75,7 +75,7 @@ config PCI_KEYSTONE config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" depends on PCI - depends on OF && (ARM || ARCH_LAYERSCAPE) + depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select MFD_SYSCON select PCIE_DW_HOST @@ -83,7 +83,7 @@ config PCI_LAYERSCAPE Say Y here if you want PCIe controller support on Layerscape SoCs. config PCI_HISI - depends on OF && ARM64 + depends on OF && (ARM64 || COMPILE_TEST) bool "HiSilicon Hip05 and Hip06 SoCs PCIe controllers" depends on PCI depends on PCI_MSI_IRQ_DOMAIN @@ -96,7 +96,7 @@ config PCI_HISI config PCIE_QCOM bool "Qualcomm PCIe controller" depends on PCI - depends on ARCH_QCOM && OF + depends on (ARCH_QCOM || COMPILE_TEST) && OF depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -108,7 +108,7 @@ config PCIE_QCOM config PCIE_ARMADA_8K bool "Marvell Armada-8K PCIe controller" depends on PCI - depends on ARCH_MVEBU + depends on ARCH_MVEBU || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST @@ -121,7 +121,7 @@ config PCIE_ARMADA_8K config PCIE_ARTPEC6 bool "Axis ARTPEC-6 PCIe controller" depends on PCI - depends on MACH_ARTPEC6 + depends on MACH_ARTPEC6 || COMPILE_TEST depends on PCI_MSI_IRQ_DOMAIN select PCIEPORTBUS select PCIE_DW_HOST diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 3708bd6..c6fef0a 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -499,9 +499,9 @@ static int dra7xx_pcie_suspend(struct device *dev) u32 val; /* clear MSE */ - val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND); + val = dw_pcie_read_dbi(pci, base, PCI_COMMAND, 0x4); val &= ~PCI_COMMAND_MEMORY; - dw_pcie_writel_dbi(pci, base, PCI_COMMAND, val); + dw_pcie_write_dbi(pci, base, PCI_COMMAND, 0x4, val); return 0; } @@ -514,9 +514,9 @@ static int dra7xx_pcie_resume(struct device *dev) u32 val; /* set MSE */ - val = dw_pcie_readl_dbi(pci, base, PCI_COMMAND); + val =
Re: [PATCH v2 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
Às 9:52 AM de 3/7/2017, Kishon Vijay Abraham I escreveu: > Previously dbi accessors can be used to access data of size 4 > bytes. But there might be situations (like accessing > MSI_MESSAGE_CONTROL in order to set/get the number of required > MSI interrupts in EP mode) where dbi accessors must > be used to access data of size 2. This is in preparation for > adding endpoint mode support to designware driver. > > Cc: Jingoo Han> Cc: Richard Zhu > Cc: Lucas Stach > Cc: Murali Karicheri > Cc: Thomas Petazzoni > Cc: Niklas Cassel > Cc: Jesper Nilsson > Cc: Joao Pinto > Cc: Zhou Wang > Cc: Gabriele Paoloni > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/pci/dwc/Kconfig| 18 > drivers/pci/dwc/pci-dra7xx.c |8 ++-- > drivers/pci/dwc/pci-exynos.c | 16 +++ > drivers/pci/dwc/pci-imx6.c | 54 +++--- > drivers/pci/dwc/pci-keystone-dw.c | 13 +++--- > drivers/pci/dwc/pcie-armada8k.c| 38 > drivers/pci/dwc/pcie-artpec6.c |6 +-- > drivers/pci/dwc/pcie-designware-host.c | 18 > drivers/pci/dwc/pcie-designware.c | 77 > +++- > drivers/pci/dwc/pcie-designware.h | 14 +++--- > drivers/pci/dwc/pcie-hisi.c| 14 +++--- > 11 files changed, 147 insertions(+), 129 deletions(-) > > diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig > index dfb8a69..cb3d5d0 100644 > --- a/drivers/pci/dwc/Kconfig > +++ b/drivers/pci/dwc/Kconfig > @@ -36,7 +36,7 @@ config PCIE_DW_PLAT > config PCI_EXYNOS > bool "Samsung Exynos PCIe controller" > depends on PCI > - depends on SOC_EXYNOS5440 > + depends on SOC_EXYNOS5440 || COMPILE_TEST Kishon, I have the idea that Bjorn suggested some time ago not to use COMPILE_TEST, because there were some problems in some drivers that needed specific arch stuff. Bjorn: Could you please confirm? Thanks.
Re: [PATCH v2 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
Às 9:52 AM de 3/7/2017, Kishon Vijay Abraham I escreveu: > Previously dbi accessors can be used to access data of size 4 > bytes. But there might be situations (like accessing > MSI_MESSAGE_CONTROL in order to set/get the number of required > MSI interrupts in EP mode) where dbi accessors must > be used to access data of size 2. This is in preparation for > adding endpoint mode support to designware driver. > > Cc: Jingoo Han > Cc: Richard Zhu > Cc: Lucas Stach > Cc: Murali Karicheri > Cc: Thomas Petazzoni > Cc: Niklas Cassel > Cc: Jesper Nilsson > Cc: Joao Pinto > Cc: Zhou Wang > Cc: Gabriele Paoloni > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/pci/dwc/Kconfig| 18 > drivers/pci/dwc/pci-dra7xx.c |8 ++-- > drivers/pci/dwc/pci-exynos.c | 16 +++ > drivers/pci/dwc/pci-imx6.c | 54 +++--- > drivers/pci/dwc/pci-keystone-dw.c | 13 +++--- > drivers/pci/dwc/pcie-armada8k.c| 38 > drivers/pci/dwc/pcie-artpec6.c |6 +-- > drivers/pci/dwc/pcie-designware-host.c | 18 > drivers/pci/dwc/pcie-designware.c | 77 > +++- > drivers/pci/dwc/pcie-designware.h | 14 +++--- > drivers/pci/dwc/pcie-hisi.c| 14 +++--- > 11 files changed, 147 insertions(+), 129 deletions(-) > > diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig > index dfb8a69..cb3d5d0 100644 > --- a/drivers/pci/dwc/Kconfig > +++ b/drivers/pci/dwc/Kconfig > @@ -36,7 +36,7 @@ config PCIE_DW_PLAT > config PCI_EXYNOS > bool "Samsung Exynos PCIe controller" > depends on PCI > - depends on SOC_EXYNOS5440 > + depends on SOC_EXYNOS5440 || COMPILE_TEST Kishon, I have the idea that Bjorn suggested some time ago not to use COMPILE_TEST, because there were some problems in some drivers that needed specific arch stuff. Bjorn: Could you please confirm? Thanks.
Re: [PATCH v2 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
On Tuesday 07 March 2017 04:48 PM, Joao Pinto wrote: > Às 9:52 AM de 3/7/2017, Kishon Vijay Abraham I escreveu: >> Previously dbi accessors can be used to access data of size 4 >> bytes. But there might be situations (like accessing >> MSI_MESSAGE_CONTROL in order to set/get the number of required >> MSI interrupts in EP mode) where dbi accessors must >> be used to access data of size 2. This is in preparation for >> adding endpoint mode support to designware driver. >> >> Cc: Jingoo Han>> Cc: Richard Zhu >> Cc: Lucas Stach >> Cc: Murali Karicheri >> Cc: Thomas Petazzoni >> Cc: Niklas Cassel >> Cc: Jesper Nilsson >> Cc: Joao Pinto >> Cc: Zhou Wang >> Cc: Gabriele Paoloni >> Signed-off-by: Kishon Vijay Abraham I >> --- >> drivers/pci/dwc/Kconfig| 18 >> drivers/pci/dwc/pci-dra7xx.c |8 ++-- >> drivers/pci/dwc/pci-exynos.c | 16 +++ >> drivers/pci/dwc/pci-imx6.c | 54 +++--- >> drivers/pci/dwc/pci-keystone-dw.c | 13 +++--- >> drivers/pci/dwc/pcie-armada8k.c| 38 >> drivers/pci/dwc/pcie-artpec6.c |6 +-- >> drivers/pci/dwc/pcie-designware-host.c | 18 >> drivers/pci/dwc/pcie-designware.c | 77 >> +++- >> drivers/pci/dwc/pcie-designware.h | 14 +++--- >> drivers/pci/dwc/pcie-hisi.c| 14 +++--- >> 11 files changed, 147 insertions(+), 129 deletions(-) >> >> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig >> index dfb8a69..cb3d5d0 100644 >> --- a/drivers/pci/dwc/Kconfig >> +++ b/drivers/pci/dwc/Kconfig >> @@ -36,7 +36,7 @@ config PCIE_DW_PLAT >> config PCI_EXYNOS >> bool "Samsung Exynos PCIe controller" >> depends on PCI >> -depends on SOC_EXYNOS5440 >> +depends on SOC_EXYNOS5440 || COMPILE_TEST > > Kishon, I have the idea that Bjorn suggested some time ago not to use > COMPILE_TEST, because there were some problems in some drivers that needed > specific arch stuff. sigh.. this spilled through from my testing. This Kconfig changes was un-intentional. Thanks Kishon
Re: [PATCH v2 5/7] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes
On Tuesday 07 March 2017 04:48 PM, Joao Pinto wrote: > Às 9:52 AM de 3/7/2017, Kishon Vijay Abraham I escreveu: >> Previously dbi accessors can be used to access data of size 4 >> bytes. But there might be situations (like accessing >> MSI_MESSAGE_CONTROL in order to set/get the number of required >> MSI interrupts in EP mode) where dbi accessors must >> be used to access data of size 2. This is in preparation for >> adding endpoint mode support to designware driver. >> >> Cc: Jingoo Han >> Cc: Richard Zhu >> Cc: Lucas Stach >> Cc: Murali Karicheri >> Cc: Thomas Petazzoni >> Cc: Niklas Cassel >> Cc: Jesper Nilsson >> Cc: Joao Pinto >> Cc: Zhou Wang >> Cc: Gabriele Paoloni >> Signed-off-by: Kishon Vijay Abraham I >> --- >> drivers/pci/dwc/Kconfig| 18 >> drivers/pci/dwc/pci-dra7xx.c |8 ++-- >> drivers/pci/dwc/pci-exynos.c | 16 +++ >> drivers/pci/dwc/pci-imx6.c | 54 +++--- >> drivers/pci/dwc/pci-keystone-dw.c | 13 +++--- >> drivers/pci/dwc/pcie-armada8k.c| 38 >> drivers/pci/dwc/pcie-artpec6.c |6 +-- >> drivers/pci/dwc/pcie-designware-host.c | 18 >> drivers/pci/dwc/pcie-designware.c | 77 >> +++- >> drivers/pci/dwc/pcie-designware.h | 14 +++--- >> drivers/pci/dwc/pcie-hisi.c| 14 +++--- >> 11 files changed, 147 insertions(+), 129 deletions(-) >> >> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig >> index dfb8a69..cb3d5d0 100644 >> --- a/drivers/pci/dwc/Kconfig >> +++ b/drivers/pci/dwc/Kconfig >> @@ -36,7 +36,7 @@ config PCIE_DW_PLAT >> config PCI_EXYNOS >> bool "Samsung Exynos PCIe controller" >> depends on PCI >> -depends on SOC_EXYNOS5440 >> +depends on SOC_EXYNOS5440 || COMPILE_TEST > > Kishon, I have the idea that Bjorn suggested some time ago not to use > COMPILE_TEST, because there were some problems in some drivers that needed > specific arch stuff. sigh.. this spilled through from my testing. This Kconfig changes was un-intentional. Thanks Kishon