Re: [PATCH v2 6/9] clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d

[Stephen Boyd]

Quoting AngeloGioacchino Del Regno (2021-01-13 10:38:14)
> In commit 734bdefdb043 ("clk: qcom: rcg2: Stop hardcoding gfx3d
> pingpong parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops)
> were generalized in order to be able to reuse the same ops for
> more than just one clock for one SoC: follow the change here in
> the MSM8996 MMCC.
> 
> Signed-off-by: AngeloGioacchino Del Regno 
> 
> ---

Applied to clk-next

Re: [PATCH v2 6/9] clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d

[Bjorn Andersson]

On Wed 13 Jan 12:38 CST 2021, AngeloGioacchino Del Regno wrote:

> In commit 734bdefdb043 ("clk: qcom: rcg2: Stop hardcoding gfx3d
> pingpong parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops)

I believe you're referring to patch 5 here, which when merged won't have
this hash. So you'd need to say "in the previous commit (...)" or
something like that.

Regards,
Bjorn

> were generalized in order to be able to reuse the same ops for
> more than just one clock for one SoC: follow the change here in
> the MSM8996 MMCC.
> 
> Signed-off-by: AngeloGioacchino Del Regno 
> 
> ---
>  drivers/clk/qcom/mmcc-msm8996.c | 29 ++---
>  1 file changed, 18 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
> index 3b3aac07fb2d..24843e4f2599 100644
> --- a/drivers/clk/qcom/mmcc-msm8996.c
> +++ b/drivers/clk/qcom/mmcc-msm8996.c
> @@ -528,16 +528,23 @@ static struct clk_rcg2 maxi_clk_src = {
>   },
>  };
>  
> -static struct clk_rcg2 gfx3d_clk_src = {
> - .cmd_rcgr = 0x4000,
> - .hid_width = 5,
> - .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
> - .clkr.hw.init = &(struct clk_init_data){
> - .name = "gfx3d_clk_src",
> - .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
> - .num_parents = 6,
> - .ops = _gfx3d_ops,
> - .flags = CLK_SET_RATE_PARENT,
> +static struct clk_rcg2_gfx3d gfx3d_clk_src = {
> + .rcg = {
> + .cmd_rcgr = 0x4000,
> + .hid_width = 5,
> + .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gfx3d_clk_src",
> + .parent_names = 
> mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
> + .num_parents = 6,
> + .ops = _gfx3d_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> + },
> + .hws = (struct clk_hw*[]) {
> + ,
> + ,
> + 
>   },
>  };
>  
> @@ -3089,7 +3096,7 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = {
>   [AHB_CLK_SRC] = _clk_src.clkr,
>   [AXI_CLK_SRC] = _clk_src.clkr,
>   [MAXI_CLK_SRC] = _clk_src.clkr,
> - [GFX3D_CLK_SRC] = _clk_src.clkr,
> + [GFX3D_CLK_SRC] = _clk_src.rcg.clkr,
>   [RBBMTIMER_CLK_SRC] = _clk_src.clkr,
>   [ISENSE_CLK_SRC] = _clk_src.clkr,
>   [RBCPR_CLK_SRC] = _clk_src.clkr,
> -- 
> 2.29.2
> 

[PATCH v2 6/9] clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d

[AngeloGioacchino Del Regno]

In commit 734bdefdb043 ("clk: qcom: rcg2: Stop hardcoding gfx3d
pingpong parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops)
were generalized in order to be able to reuse the same ops for
more than just one clock for one SoC: follow the change here in
the MSM8996 MMCC.

Signed-off-by: AngeloGioacchino Del Regno 

---
 drivers/clk/qcom/mmcc-msm8996.c | 29 ++---
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/qcom/mmcc-msm8996.c b/drivers/clk/qcom/mmcc-msm8996.c
index 3b3aac07fb2d..24843e4f2599 100644
--- a/drivers/clk/qcom/mmcc-msm8996.c
+++ b/drivers/clk/qcom/mmcc-msm8996.c
@@ -528,16 +528,23 @@ static struct clk_rcg2 maxi_clk_src = {
},
 };
 
-static struct clk_rcg2 gfx3d_clk_src = {
-   .cmd_rcgr = 0x4000,
-   .hid_width = 5,
-   .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
-   .clkr.hw.init = &(struct clk_init_data){
-   .name = "gfx3d_clk_src",
-   .parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
-   .num_parents = 6,
-   .ops = _gfx3d_ops,
-   .flags = CLK_SET_RATE_PARENT,
+static struct clk_rcg2_gfx3d gfx3d_clk_src = {
+   .rcg = {
+   .cmd_rcgr = 0x4000,
+   .hid_width = 5,
+   .parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
+   .clkr.hw.init = &(struct clk_init_data){
+   .name = "gfx3d_clk_src",
+   .parent_names = 
mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
+   .num_parents = 6,
+   .ops = _gfx3d_ops,
+   .flags = CLK_SET_RATE_PARENT,
+   },
+   },
+   .hws = (struct clk_hw*[]) {
+   ,
+   ,
+   
},
 };
 
@@ -3089,7 +3096,7 @@ static struct clk_regmap *mmcc_msm8996_clocks[] = {
[AHB_CLK_SRC] = _clk_src.clkr,
[AXI_CLK_SRC] = _clk_src.clkr,
[MAXI_CLK_SRC] = _clk_src.clkr,
-   [GFX3D_CLK_SRC] = _clk_src.clkr,
+   [GFX3D_CLK_SRC] = _clk_src.rcg.clkr,
[RBBMTIMER_CLK_SRC] = _clk_src.clkr,
[ISENSE_CLK_SRC] = _clk_src.clkr,
[RBCPR_CLK_SRC] = _clk_src.clkr,
-- 
2.29.2