Re: [PATCH v3] thermal: exynos: Add TMU support for Exynos7 SoC
Hi Lukasz, On Mon, Jan 19, 2015 at 6:34 PM, Lukasz Majewski wrote: > Hi Abhilash, > >> Add registers, bit fields and compatible strings for Exynos7 TMU >> (Thermal Management Unit). Following are a few of the differences >> in the Exynos7 TMU from earlier SoCs: >> - 8 trigger levels >> - Different bit offsets and more registers for the rising >> and falling thresholds. >> - New power down detection bit in the TMU_CONTROL register >> which does not update the CURRENT_TEMP0 when tmu power down >> is detected. >> - Change in bit offset for the NEXT_DATA field of EMUL_CON >> register. EMUL_CON register address has also changed. >> - INTSTAT and INTCLEAR registers present in earlier SoCs >> have been combined into one INTPEND register. The register >> address for INTCLEAR and INTPEND is also different. >> - Since there are 8 rising/falling interrupts as against >> at most 4 in earlier SoCs the INTEN bit offsets are different. >> - Multiple probe support which is handled by a TMU_CONTROL1 >> register (No support for this in the current patch). >> >> This patch adds special clock support required only for Exynos7 >> and updates the bindings documentation appropriately. It also updates >> the "code_to_temp" prototype as Exynos7 has 9 bit code-temp mapping. >> >> Signed-off-by: Abhilash Kesavan >> --- >> This patch is based on Lukasz Majewski's Exynos TMU v4 patchset: >> http://www.spinics.net/lists/linux-samsung-soc/msg41183.html >> >> Changes since v2: >> - Rebased on top of Lukasz' latest exynos tmu series (v4). >> - Added new exynos7 soc_type. >> Changes since v1: >> - Rebased on top of Lukasz' latest exynos tmu series (v2). >> - Added sclk support to patch adding Exynos7 tmu support. >> Previously, it was a separate patch. >> - Used the SOC type to decide if sclk is present. >> >> .../devicetree/bindings/thermal/exynos-thermal.txt |4 + >> drivers/thermal/samsung/exynos_tmu.c | 203 >> +++- >> drivers/thermal/samsung/exynos_tmu.h |1 + 3 files >> changed, 199 insertions(+), 9 deletions(-) >> >> diff --git >> a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt >> b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index >> 0f44932..695150a 100644 --- >> a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ >> b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ >> -12,6 +12,7 @@ "samsung,exynos5420-tmu-ext-triminfo" for TMU channels >> 2, 3 and 4 Exynos5420 (Must pass triminfo base and triminfo clock) >> "samsung,exynos5440-tmu" >> +"samsung,exynos7-tmu" >> - interrupt-parent : The phandle for the interrupt controller >> - reg : Address range of the thermal registers. For soc's which has >> multiple instances of TMU and some registers are shared across all >> TMU's like @@ -32,10 +33,13 @@ >> - clocks : The main clocks for TMU device >> -- 1. operational clock for TMU channel >> -- 2. optional clock to access the shared registers of TMU >> channel >> + -- 3. optional special clock for functional operation >> - clock-names : Thermal system clock name >> -- "tmu_apbif" operational clock for current TMU channel >> -- "tmu_triminfo_apbif" clock to access the shared triminfo >> register for current TMU channel >> + -- "tmu_sclk" clock for functional operation of the current >> TMU >> + channel >> - vtmu-supply: This entry is optional and provides the regulator >> node supplying voltage to TMU. If needed this entry can be placed >> inside board/platform specific dts file. > > I would recommend splitting the documentation from the code. IMHO it > would be more readable. I will split the documentation out into a separate patch. > >> diff --git a/drivers/thermal/samsung/exynos_tmu.c >> b/drivers/thermal/samsung/exynos_tmu.c index 633a9e2..8b26acb 100644 >> --- a/drivers/thermal/samsung/exynos_tmu.c >> +++ b/drivers/thermal/samsung/exynos_tmu.c >> @@ -119,6 +119,26 @@ >> #define EXYNOS5440_TMU_TH_RISE4_SHIFT24 >> #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 >> >> +/* Exynos7 specific registers */ >> +#define EXYNOS7_THD_TEMP_RISE7_6 0x50 >> +#define EXYNOS7_THD_TEMP_FALL7_6 0x60 >> +#define EXYNOS7_TMU_REG_INTEN0x110 >> +#define EXYNOS7_TMU_REG_INTPEND 0x118 > ^ I suppose that > this misalignment is > only done by my mail > client and checkpatch > is not complaining. I re-ran checkpatch and it did not report any warnings, so perhaps it is your e-mail client. >> +#define EXYNOS
Re: [PATCH v3] thermal: exynos: Add TMU support for Exynos7 SoC
Hi Abhilash, > Add registers, bit fields and compatible strings for Exynos7 TMU > (Thermal Management Unit). Following are a few of the differences > in the Exynos7 TMU from earlier SoCs: > - 8 trigger levels > - Different bit offsets and more registers for the rising > and falling thresholds. > - New power down detection bit in the TMU_CONTROL register > which does not update the CURRENT_TEMP0 when tmu power down > is detected. > - Change in bit offset for the NEXT_DATA field of EMUL_CON > register. EMUL_CON register address has also changed. > - INTSTAT and INTCLEAR registers present in earlier SoCs > have been combined into one INTPEND register. The register > address for INTCLEAR and INTPEND is also different. > - Since there are 8 rising/falling interrupts as against > at most 4 in earlier SoCs the INTEN bit offsets are different. > - Multiple probe support which is handled by a TMU_CONTROL1 > register (No support for this in the current patch). > > This patch adds special clock support required only for Exynos7 > and updates the bindings documentation appropriately. It also updates > the "code_to_temp" prototype as Exynos7 has 9 bit code-temp mapping. > > Signed-off-by: Abhilash Kesavan > --- > This patch is based on Lukasz Majewski's Exynos TMU v4 patchset: > http://www.spinics.net/lists/linux-samsung-soc/msg41183.html > > Changes since v2: > - Rebased on top of Lukasz' latest exynos tmu series (v4). > - Added new exynos7 soc_type. > Changes since v1: > - Rebased on top of Lukasz' latest exynos tmu series (v2). > - Added sclk support to patch adding Exynos7 tmu support. > Previously, it was a separate patch. > - Used the SOC type to decide if sclk is present. > > .../devicetree/bindings/thermal/exynos-thermal.txt |4 + > drivers/thermal/samsung/exynos_tmu.c | 203 > +++- > drivers/thermal/samsung/exynos_tmu.h |1 + 3 files > changed, 199 insertions(+), 9 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt > b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index > 0f44932..695150a 100644 --- > a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ > b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ > -12,6 +12,7 @@ "samsung,exynos5420-tmu-ext-triminfo" for TMU channels > 2, 3 and 4 Exynos5420 (Must pass triminfo base and triminfo clock) > "samsung,exynos5440-tmu" > +"samsung,exynos7-tmu" > - interrupt-parent : The phandle for the interrupt controller > - reg : Address range of the thermal registers. For soc's which has > multiple instances of TMU and some registers are shared across all > TMU's like @@ -32,10 +33,13 @@ > - clocks : The main clocks for TMU device > -- 1. operational clock for TMU channel > -- 2. optional clock to access the shared registers of TMU > channel > + -- 3. optional special clock for functional operation > - clock-names : Thermal system clock name > -- "tmu_apbif" operational clock for current TMU channel > -- "tmu_triminfo_apbif" clock to access the shared triminfo > register for current TMU channel > + -- "tmu_sclk" clock for functional operation of the current > TMU > + channel > - vtmu-supply: This entry is optional and provides the regulator > node supplying voltage to TMU. If needed this entry can be placed > inside board/platform specific dts file. I would recommend splitting the documentation from the code. IMHO it would be more readable. > diff --git a/drivers/thermal/samsung/exynos_tmu.c > b/drivers/thermal/samsung/exynos_tmu.c index 633a9e2..8b26acb 100644 > --- a/drivers/thermal/samsung/exynos_tmu.c > +++ b/drivers/thermal/samsung/exynos_tmu.c > @@ -119,6 +119,26 @@ > #define EXYNOS5440_TMU_TH_RISE4_SHIFT24 > #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 > > +/* Exynos7 specific registers */ > +#define EXYNOS7_THD_TEMP_RISE7_6 0x50 > +#define EXYNOS7_THD_TEMP_FALL7_6 0x60 > +#define EXYNOS7_TMU_REG_INTEN0x110 > +#define EXYNOS7_TMU_REG_INTPEND 0x118 ^ I suppose that this misalignment is only done by my mail client and checkpatch is not complaining. > +#define EXYNOS7_TMU_REG_EMUL_CON 0x160 > + > +#define EXYNOS7_TMU_TEMP_MASK0x1ff > +#define EXYNOS7_PD_DET_EN_SHIFT 23 > +#define EXYNOS7_TMU_INTEN_RISE0_SHIFT0 > +#define EXYNOS7_TMU_INTEN_RISE1_SHIFT1 > +#define EXYNOS7_TMU_INTEN_RISE2_SHIFT
[PATCH v3] thermal: exynos: Add TMU support for Exynos7 SoC
Add registers, bit fields and compatible strings for Exynos7 TMU (Thermal Management Unit). Following are a few of the differences in the Exynos7 TMU from earlier SoCs: - 8 trigger levels - Different bit offsets and more registers for the rising and falling thresholds. - New power down detection bit in the TMU_CONTROL register which does not update the CURRENT_TEMP0 when tmu power down is detected. - Change in bit offset for the NEXT_DATA field of EMUL_CON register. EMUL_CON register address has also changed. - INTSTAT and INTCLEAR registers present in earlier SoCs have been combined into one INTPEND register. The register address for INTCLEAR and INTPEND is also different. - Since there are 8 rising/falling interrupts as against at most 4 in earlier SoCs the INTEN bit offsets are different. - Multiple probe support which is handled by a TMU_CONTROL1 register (No support for this in the current patch). This patch adds special clock support required only for Exynos7 and updates the bindings documentation appropriately. It also updates the "code_to_temp" prototype as Exynos7 has 9 bit code-temp mapping. Signed-off-by: Abhilash Kesavan --- This patch is based on Lukasz Majewski's Exynos TMU v4 patchset: http://www.spinics.net/lists/linux-samsung-soc/msg41183.html Changes since v2: - Rebased on top of Lukasz' latest exynos tmu series (v4). - Added new exynos7 soc_type. Changes since v1: - Rebased on top of Lukasz' latest exynos tmu series (v2). - Added sclk support to patch adding Exynos7 tmu support. Previously, it was a separate patch. - Used the SOC type to decide if sclk is present. .../devicetree/bindings/thermal/exynos-thermal.txt |4 + drivers/thermal/samsung/exynos_tmu.c | 203 +++- drivers/thermal/samsung/exynos_tmu.h |1 + 3 files changed, 199 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt index 0f44932..695150a 100644 --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt @@ -12,6 +12,7 @@ "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4 Exynos5420 (Must pass triminfo base and triminfo clock) "samsung,exynos5440-tmu" + "samsung,exynos7-tmu" - interrupt-parent : The phandle for the interrupt controller - reg : Address range of the thermal registers. For soc's which has multiple instances of TMU and some registers are shared across all TMU's like @@ -32,10 +33,13 @@ - clocks : The main clocks for TMU device -- 1. operational clock for TMU channel -- 2. optional clock to access the shared registers of TMU channel + -- 3. optional special clock for functional operation - clock-names : Thermal system clock name -- "tmu_apbif" operational clock for current TMU channel -- "tmu_triminfo_apbif" clock to access the shared triminfo register for current TMU channel + -- "tmu_sclk" clock for functional operation of the current TMU + channel - vtmu-supply: This entry is optional and provides the regulator node supplying voltage to TMU. If needed this entry can be placed inside board/platform specific dts file. diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 633a9e2..8b26acb 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -119,6 +119,26 @@ #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 +/* Exynos7 specific registers */ +#define EXYNOS7_THD_TEMP_RISE7_6 0x50 +#define EXYNOS7_THD_TEMP_FALL7_6 0x60 +#define EXYNOS7_TMU_REG_INTEN 0x110 +#define EXYNOS7_TMU_REG_INTPEND0x118 +#define EXYNOS7_TMU_REG_EMUL_CON 0x160 + +#define EXYNOS7_TMU_TEMP_MASK 0x1ff +#define EXYNOS7_PD_DET_EN_SHIFT23 +#define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 +#define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1 +#define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2 +#define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3 +#define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4 +#define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5 +#define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6 +#define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7 +#define EXYNOS7_EMUL_DATA_SHIFT7 +#define EXYNOS7_EMUL_DATA_MASK 0x1ff + #define MCELSIUS 1000 /** * struct exynos_tmu_data : A structure to hold the private data of the TMU @@ -133,6 +153,7 @@ * @lock:
