[PATCH v3 06/34] dt-bindings: Add bindings for Keem Bay VPU IPC driver

2021-01-30 Thread mgross 
From: Paul Murphy 

Add DT bindings documentation for the Keem Bay VPU IPC driver.

Cc: Rob Herring 
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross 
Signed-off-by: Paul Murphy 
Co-developed-by: Daniele Alessandrelli 
Signed-off-by: Daniele Alessandrelli 
---
 .../soc/intel/intel,keembay-vpu-ipc.yaml  | 153 ++
 1 file changed, 153 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml

diff --git 
a/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml 
b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
new file mode 100644
index ..cd1c4abe8bc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) Intel Corporation. All rights reserved.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-vpu-ipc.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Keem Bay VPU IPC
+
+maintainers:
+  - Paul Murphy 
+
+description:
+  The VPU IPC driver facilitates loading of firmware, control, and 
communication
+  with the VPU over the IPC FIFO in the Intel Keem Bay SoC.
+
+properties:
+  compatible:
+oneOf:
+  - items:
+- const: intel,keembay-vpu-ipc
+
+  reg:
+items:
+  - description: NCE WDT registers
+  - description: NCE TIM_GEN_CONFIG registers
+  - description: MSS WDT registers
+  - description: MSS TIM_GEN_CONFIG registers
+
+  reg-names:
+items:
+  - const: nce_wdt
+  - const: nce_tim_cfg
+  - const: mss_wdt
+  - const: mss_tim_cfg
+
+  memory-region:
+items:
+  - description: reference to the VPU reserved memory region
+  - description: reference to the X509 reserved memory region
+  - description: reference to the MSS IPC area
+
+  clocks:
+items:
+  - description: cpu clock
+  - description: pll 0 out 0 rate
+  - description: pll 0 out 1 rate
+  - description: pll 0 out 2 rate
+  - description: pll 0 out 3 rate
+  - description: pll 1 out 0 rate
+  - description: pll 1 out 1 rate
+  - description: pll 1 out 2 rate
+  - description: pll 1 out 3 rate
+  - description: pll 2 out 0 rate
+  - description: pll 2 out 1 rate
+  - description: pll 2 out 2 rate
+  - description: pll 2 out 3 rate
+
+  clock-names:
+items:
+  - const: cpu_clock
+  - const: pll_0_out_0
+  - const: pll_0_out_1
+  - const: pll_0_out_2
+  - const: pll_0_out_3
+  - const: pll_1_out_0
+  - const: pll_1_out_1
+  - const: pll_1_out_2
+  - const: pll_1_out_3
+  - const: pll_2_out_0
+  - const: pll_2_out_1
+  - const: pll_2_out_2
+  - const: pll_2_out_3
+
+  interrupts:
+items:
+  - description: number of NCE sub-system WDT timeout IRQ
+  - description: number of MSS sub-system WDT timeout IRQ
+
+  interrupt-names:
+items:
+  - const: nce_wdt
+  - const: mss_wdt
+
+  intel,keembay-vpu-ipc-nce-wdt-redirect:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+  Number to which we will request that the NCE sub-system
+  re-directs it's WDT timeout IRQ
+
+  intel,keembay-vpu-ipc-mss-wdt-redirect:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+  Number to which we will request that the MSS sub-system
+  re-directs it's WDT timeout IRQ
+
+  intel,keembay-vpu-ipc-imr:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+  IMR (isolated memory region) number which we will request
+  the runtime service uses to protect the VPU memory region
+  before authentication
+
+  intel,keembay-vpu-ipc-id:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description: The VPU ID to be passed to the VPU firmware.
+
+additionalProperties: False
+
+examples:
+  - |
+#include 
+vpu-ipc@3f00209c {
+compatible = "intel,keembay-vpu-ipc";
+reg = <0x3f00209c 0x10>,
+  <0x3f003008 0x4>,
+  <0x2082009c 0x10>,
+  <0x20821008 0x4>;
+reg-names = "nce_wdt",
+"nce_tim_cfg",
+"mss_wdt",
+"mss_tim_cfg";
+memory-region = <&vpu_reserved>,
+<&vpu_x509_reserved>,
+<&mss_ipc_reserved>;
+clocks = <&scmi_clk 0>,
+ <&scmi_clk 0>,
+ <&scmi_clk 1>,
+ <&scmi_clk 2>,
+ <&scmi_clk 3>,
+ <&scmi_clk 4>,
+ <&scmi_clk 5>,
+ <&scmi_clk 6>,
+ <&scmi_clk 7>,
+ <&scmi_clk 8>,
+ <&scmi_clk 9>,
+ <&scmi_clk 10>,
+ <&scmi_clk 11>;
+clock-names = "cpu_clock",
+  "pll_0_out_0", "pll_0_out_1",
+

Re: [PATCH v3 06/34] dt-bindings: Add bindings for Keem Bay VPU IPC driver

2021-01-29 Thread mark gross 
On Wed, Jan 27, 2021 at 08:00:11AM -0600, Rob Herring wrote:
> On Mon, 25 Jan 2021 21:40:08 -0800, mgr...@linux.intel.com wrote:
> > From: Paul Murphy 
> > 
> > Add DT bindings documentation for the Keem Bay VPU IPC driver.
> > 
> > Cc: Rob Herring 
> > Cc: devicet...@vger.kernel.org
> > Reviewed-by: Mark Gross 
> > Signed-off-by: Paul Murphy 
> > Co-developed-by: Daniele Alessandrelli 
> > Signed-off-by: Daniele Alessandrelli 
> > ---
> >  .../soc/intel/intel,keembay-vpu-ipc.yaml  | 153 ++
> >  1 file changed, 153 insertions(+)
> >  create mode 100644 
> > Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
> > 
> 
> My bot found errors running 'make dt_binding_check' on your patch:
> 
> yamllint warnings/errors:
> ./Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml:21:9:
>  [warning] wrong indentation: expected 10 but found 8 (indentation)
> 
> dtschema/dtc warnings/errors:
fixed.


> 
> See https://patchwork.ozlabs.org/patch/1432168
> 
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit.
>

Re: [PATCH v3 06/34] dt-bindings: Add bindings for Keem Bay VPU IPC driver

2021-01-27 Thread Rob Herring 
On Mon, 25 Jan 2021 21:40:08 -0800, mgr...@linux.intel.com wrote:
> From: Paul Murphy 
> 
> Add DT bindings documentation for the Keem Bay VPU IPC driver.
> 
> Cc: Rob Herring 
> Cc: devicet...@vger.kernel.org
> Reviewed-by: Mark Gross 
> Signed-off-by: Paul Murphy 
> Co-developed-by: Daniele Alessandrelli 
> Signed-off-by: Daniele Alessandrelli 
> ---
>  .../soc/intel/intel,keembay-vpu-ipc.yaml  | 153 ++
>  1 file changed, 153 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml:21:9: 
[warning] wrong indentation: expected 10 but found 8 (indentation)

dtschema/dtc warnings/errors:

See https://patchwork.ozlabs.org/patch/1432168

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

[PATCH v3 06/34] dt-bindings: Add bindings for Keem Bay VPU IPC driver

2021-01-26 Thread mgross 
From: Paul Murphy 

Add DT bindings documentation for the Keem Bay VPU IPC driver.

Cc: Rob Herring 
Cc: devicet...@vger.kernel.org
Reviewed-by: Mark Gross 
Signed-off-by: Paul Murphy 
Co-developed-by: Daniele Alessandrelli 
Signed-off-by: Daniele Alessandrelli 
---
 .../soc/intel/intel,keembay-vpu-ipc.yaml  | 153 ++
 1 file changed, 153 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml

diff --git 
a/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml 
b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
new file mode 100644
index ..cd1c4abe8bc9
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/intel/intel,keembay-vpu-ipc.yaml
@@ -0,0 +1,153 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) Intel Corporation. All rights reserved.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/intel/intel,keembay-vpu-ipc.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Intel Keem Bay VPU IPC
+
+maintainers:
+  - Paul Murphy 
+
+description:
+  The VPU IPC driver facilitates loading of firmware, control, and 
communication
+  with the VPU over the IPC FIFO in the Intel Keem Bay SoC.
+
+properties:
+  compatible:
+oneOf:
+  - items:
+- const: intel,keembay-vpu-ipc
+
+  reg:
+items:
+  - description: NCE WDT registers
+  - description: NCE TIM_GEN_CONFIG registers
+  - description: MSS WDT registers
+  - description: MSS TIM_GEN_CONFIG registers
+
+  reg-names:
+items:
+  - const: nce_wdt
+  - const: nce_tim_cfg
+  - const: mss_wdt
+  - const: mss_tim_cfg
+
+  memory-region:
+items:
+  - description: reference to the VPU reserved memory region
+  - description: reference to the X509 reserved memory region
+  - description: reference to the MSS IPC area
+
+  clocks:
+items:
+  - description: cpu clock
+  - description: pll 0 out 0 rate
+  - description: pll 0 out 1 rate
+  - description: pll 0 out 2 rate
+  - description: pll 0 out 3 rate
+  - description: pll 1 out 0 rate
+  - description: pll 1 out 1 rate
+  - description: pll 1 out 2 rate
+  - description: pll 1 out 3 rate
+  - description: pll 2 out 0 rate
+  - description: pll 2 out 1 rate
+  - description: pll 2 out 2 rate
+  - description: pll 2 out 3 rate
+
+  clock-names:
+items:
+  - const: cpu_clock
+  - const: pll_0_out_0
+  - const: pll_0_out_1
+  - const: pll_0_out_2
+  - const: pll_0_out_3
+  - const: pll_1_out_0
+  - const: pll_1_out_1
+  - const: pll_1_out_2
+  - const: pll_1_out_3
+  - const: pll_2_out_0
+  - const: pll_2_out_1
+  - const: pll_2_out_2
+  - const: pll_2_out_3
+
+  interrupts:
+items:
+  - description: number of NCE sub-system WDT timeout IRQ
+  - description: number of MSS sub-system WDT timeout IRQ
+
+  interrupt-names:
+items:
+  - const: nce_wdt
+  - const: mss_wdt
+
+  intel,keembay-vpu-ipc-nce-wdt-redirect:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+  Number to which we will request that the NCE sub-system
+  re-directs it's WDT timeout IRQ
+
+  intel,keembay-vpu-ipc-mss-wdt-redirect:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+  Number to which we will request that the MSS sub-system
+  re-directs it's WDT timeout IRQ
+
+  intel,keembay-vpu-ipc-imr:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description:
+  IMR (isolated memory region) number which we will request
+  the runtime service uses to protect the VPU memory region
+  before authentication
+
+  intel,keembay-vpu-ipc-id:
+$ref: "/schemas/types.yaml#/definitions/uint32"
+description: The VPU ID to be passed to the VPU firmware.
+
+additionalProperties: False
+
+examples:
+  - |
+#include 
+vpu-ipc@3f00209c {
+compatible = "intel,keembay-vpu-ipc";
+reg = <0x3f00209c 0x10>,
+  <0x3f003008 0x4>,
+  <0x2082009c 0x10>,
+  <0x20821008 0x4>;
+reg-names = "nce_wdt",
+"nce_tim_cfg",
+"mss_wdt",
+"mss_tim_cfg";
+memory-region = <&vpu_reserved>,
+<&vpu_x509_reserved>,
+<&mss_ipc_reserved>;
+clocks = <&scmi_clk 0>,
+ <&scmi_clk 0>,
+ <&scmi_clk 1>,
+ <&scmi_clk 2>,
+ <&scmi_clk 3>,
+ <&scmi_clk 4>,
+ <&scmi_clk 5>,
+ <&scmi_clk 6>,
+ <&scmi_clk 7>,
+ <&scmi_clk 8>,
+ <&scmi_clk 9>,
+ <&scmi_clk 10>,
+ <&scmi_clk 11>;
+clock-names = "cpu_clock",
+  "pll_0_out_0", "pll_0_out_1",
+