Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
On Sat, Aug 12, 2017 at 12:51 PM, wrote: > 在 2017-08-12 12:04，Chen-Yu Tsai 写道： >> >> On Sat, Jul 22, 2017 at 11:00 AM, wrote: >>> >>> 在 2017-05-29 15:34，Chen-Yu Tsai 写道： Hi, On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote: >> >> >> [...] >> > + > +/* > + * For the special bit in gate part, please see the BSP source code at > + * > > https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/drivers/clk/sunxi/clk-sun8iw11.c#L665 > + */ > +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_sata_clk, "pll-sata", > + "osc24M", 0x034, > + 8, 5, /* N */ > + 4, 2, /* K */ > + 0, 2, /* M */ > + BIT(31) | BIT(14), /* gate */ > + BIT(28),/* lock */ > + 0); I think this is a somewhat simplified approach. From what I understand of the user manual, the SATA clock path look like: [ PLL-PERIPH0-SATA ] -\ mux @ 0x34 bit 30 --- gate @ 0x34 bit 14 --- ... [ PLL-SATA ] -/ ... from above ... --\ mux @ 0xc8 bit 24 --- gate @ 0xc8 bit 31 [ external oscillator ] -/ If you choose to simplify the implementation, please include a detailed note as to why you chose to do so, and the validity of the simplification. >>> >>> >>> >>> I think it can be fully implemented... >>> >>> But how should I call the internal clock controlled by the mux @ 0x34 bit >>> 30? >> >> >> sata-pll-mux? > > > I choose to call it pll-sata-out, as the mux @ 0x34 bit 30 is called > "PLL_OUTPUT_SEL". Cool. Note that the clock names don't really matter for end users. The only place this is visible is debugfs, or if some driver prints it out for debug messages. So the only real requirement is that the name makes some sense to any developers using it, in a way that they can spot if they are using it wrong, like accidentally using a clock for another module, and being able to roughly match it up to the datasheet. ChenYu
Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
在 2017-08-12 12:04，Chen-Yu Tsai 写道： On Sat, Jul 22, 2017 at 11:00 AM, wrote: 在 2017-05-29 15:34，Chen-Yu Tsai 写道： Hi, On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote: [...] + +/* + * For the special bit in gate part, please see the BSP source code at + * https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/drivers/clk/sunxi/clk-sun8iw11.c#L665 + */ +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_sata_clk, "pll-sata", + "osc24M", 0x034, + 8, 5, /* N */ + 4, 2, /* K */ + 0, 2, /* M */ + BIT(31) | BIT(14), /* gate */ + BIT(28),/* lock */ + 0); I think this is a somewhat simplified approach. From what I understand of the user manual, the SATA clock path look like: [ PLL-PERIPH0-SATA ] -\ mux @ 0x34 bit 30 --- gate @ 0x34 bit 14 --- ... [ PLL-SATA ] -/ ... from above ... --\ mux @ 0xc8 bit 24 --- gate @ 0xc8 bit 31 [ external oscillator ] -/ If you choose to simplify the implementation, please include a detailed note as to why you chose to do so, and the validity of the simplification. I think it can be fully implemented... But how should I call the internal clock controlled by the mux @ 0x34 bit 30? sata-pll-mux? I choose to call it pll-sata-out, as the mux @ 0x34 bit 30 is called "PLL_OUTPUT_SEL". ChenYu ___ linux-arm-kernel mailing list linux-arm-ker...@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
On Sat, Aug 12, 2017 at 12:04 PM, wrote: > 在 2017-05-29 15:34，Chen-Yu Tsai 写道： >> >> Hi, >> >> On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote: >>> >>> Allwinner R40 SoC have a clock controller module in the style of the >>> SoCs beyond sun6i, however, it's more rich and complex. >>> >>> Add support for it. >>> >>> Signed-off-by: Icenowy Zheng >>> --- >>> Changes in v3: >>> - Rebased on current linux-next. >>> Changes in v2: >>> - Fixes according to the SoC's user manual. >>> >>> drivers/clk/sunxi-ng/Kconfig | 10 + >>> drivers/clk/sunxi-ng/Makefile |1 + >>> drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 >>> + >>> drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ >>> include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + >>> include/dt-bindings/reset/sun8i-r40-ccu.h | 129 >>> 6 files changed, 1552 insertions(+) >>> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c >>> create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h >>> create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h >>> create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h >>> >> ... >>> >>> +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", >>> + "osc24M", 0x04c, >>> + 8, 7,/* N */ >> >> >> N has minimum and maximum limits. > > > These constraints are never implemented in old SoCs. Then we should implement them if we find that they are missing. ChenYu
Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
On Sat, Jul 22, 2017 at 11:00 AM, wrote: > 在 2017-05-29 15:34，Chen-Yu Tsai 写道： >> >> Hi, >> >> On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote: [...] >>> + >>> +/* >>> + * For the special bit in gate part, please see the BSP source code at >>> + * >>> https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/drivers/clk/sunxi/clk-sun8iw11.c#L665 >>> + */ >>> +static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_sata_clk, "pll-sata", >>> + "osc24M", 0x034, >>> + 8, 5, /* N */ >>> + 4, 2, /* K */ >>> + 0, 2, /* M */ >>> + BIT(31) | BIT(14), /* gate */ >>> + BIT(28),/* lock */ >>> + 0); >> >> >> I think this is a somewhat simplified approach. From what I understand >> of the user manual, the SATA clock path look like: >> >> >> [ PLL-PERIPH0-SATA ] -\ >> mux @ 0x34 bit 30 --- gate @ 0x34 bit 14 --- ... >> [ PLL-SATA ] -/ >> >> ... from above ... --\ >> mux @ 0xc8 bit 24 --- gate @ 0xc8 bit 31 >> [ external oscillator ] -/ >> >> If you choose to simplify the implementation, please include a detailed >> note as to why you chose to do so, and the validity of the simplification. > > > I think it can be fully implemented... > > But how should I call the internal clock controlled by the mux @ 0x34 bit > 30? sata-pll-mux? ChenYu
Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
在 2017-05-29 15:34，Chen-Yu Tsai 写道： Hi, On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote: Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng --- Changes in v3: - Rebased on current linux-next. Changes in v2: - Fixes according to the SoC's user manual. drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 + drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + include/dt-bindings/reset/sun8i-r40-ccu.h | 129 6 files changed, 1552 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h ... +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", + "osc24M", 0x04c, + 8, 7,/* N */ N has minimum and maximum limits. These constraints are never implemented in old SoCs. -- 2.12.2
Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
在 2017-05-29 15:34，Chen-Yu Tsai 写道： Hi, On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote: Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng --- Changes in v3: - Rebased on current linux-next. Changes in v2: - Fixes according to the SoC's user manual. drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 + drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + include/dt-bindings/reset/sun8i-r40-ccu.h | 129 6 files changed, 1552 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 67acef3d2494..c11ad3375907 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -157,6 +157,16 @@ config SUN8I_DE2_CCU select SUNXI_CCU_DIV select SUNXI_CCU_GATE +config SUN8I_R40_CCU + bool "Support for the Allwinner R40 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP You seem to be missing a few, such as CCU_GATE, CCU_MUX, CCU_PHASE. The list should at least be the same as the included headers. + default MACH_SUN8I + config SUN9I_A80_CCU bool "Support for the Allwinner A80 CCU" select SUNXI_CCU_DIV diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 0185c6ffadcb..217db667a994 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SUN8I_H3_CCU)+= ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o obj-$(CONFIG_SUN8I_DE2_CCU)+= ccu-sun8i-de2.o obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o +obj-$(CONFIG_SUN8I_R40_CCU)+= ccu-sun8i-r40.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c new file mode 100644 index ..484a8956f59c --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -0,0 +1,1153 @@ +/* + * Copyright (c) 2017 Icenowy Zheng + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun8i-r40.h" + +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", +"osc24M", 0x000, +8, 5, /* N */ +4, 2, /* K */ +0, 2, /* M */ +16, 2, /* P */ P does not do /8. Please add a limit. +BIT(31), /* gate */ +BIT(28), /* lock */ +0); + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN8I_R40_PLL_AUDIO_REG0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7,/* N */ + 0, 5,/* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", + "osc24M", 0x0010, + 8, 7, /* N */ + 0, 4,
Re: [PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
Hi, On Sat, May 27, 2017 at 06:23:06PM +0800, Icenowy Zheng wrote: > Allwinner R40 SoC have a clock controller module in the style of the > SoCs beyond sun6i, however, it's more rich and complex. > > Add support for it. > > Signed-off-by: Icenowy Zheng > --- > Changes in v3: > - Rebased on current linux-next. > Changes in v2: > - Fixes according to the SoC's user manual. > > drivers/clk/sunxi-ng/Kconfig | 10 + > drivers/clk/sunxi-ng/Makefile |1 + > drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 > + > drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ > include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + > include/dt-bindings/reset/sun8i-r40-ccu.h | 129 > 6 files changed, 1552 insertions(+) > create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h > create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h > create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h > > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig > index 67acef3d2494..c11ad3375907 100644 > --- a/drivers/clk/sunxi-ng/Kconfig > +++ b/drivers/clk/sunxi-ng/Kconfig > @@ -157,6 +157,16 @@ config SUN8I_DE2_CCU > select SUNXI_CCU_DIV > select SUNXI_CCU_GATE > > +config SUN8I_R40_CCU > + bool "Support for the Allwinner R40 CCU" > + select SUNXI_CCU_DIV > + select SUNXI_CCU_NK > + select SUNXI_CCU_NKM > + select SUNXI_CCU_NKMP > + select SUNXI_CCU_NM > + select SUNXI_CCU_MP You seem to be missing a few, such as CCU_GATE, CCU_MUX, CCU_PHASE. The list should at least be the same as the included headers. > + default MACH_SUN8I > + > config SUN9I_A80_CCU > bool "Support for the Allwinner A80 CCU" > select SUNXI_CCU_DIV > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > index 0185c6ffadcb..217db667a994 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -28,6 +28,7 @@ obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o > obj-$(CONFIG_SUN8I_DE2_CCU) += ccu-sun8i-de2.o > obj-$(CONFIG_SUN8I_R_CCU)+= ccu-sun8i-r.o > +obj-$(CONFIG_SUN8I_R40_CCU) += ccu-sun8i-r40.o > obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o > obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o > obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > new file mode 100644 > index ..484a8956f59c > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > @@ -0,0 +1,1153 @@ > +/* > + * Copyright (c) 2017 Icenowy Zheng > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include > +#include > + > +#include "ccu_common.h" > +#include "ccu_reset.h" > + > +#include "ccu_div.h" > +#include "ccu_gate.h" > +#include "ccu_mp.h" > +#include "ccu_mult.h" > +#include "ccu_nk.h" > +#include "ccu_nkm.h" > +#include "ccu_nkmp.h" > +#include "ccu_nm.h" > +#include "ccu_phase.h" > + > +#include "ccu-sun8i-r40.h" > + > +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", > + "osc24M", 0x000, > + 8, 5, /* N */ > + 4, 2, /* K */ > + 0, 2, /* M */ > + 16, 2, /* P */ P does not do /8. Please add a limit. > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +/* > + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from > + * the base (2x, 4x and 8x), and one variable divider (the one true > + * pll audio). > + * > + * We don't have any need for the variable divider for now, so we just > + * hardcode it to match with the clock names > + */ > +#define SUN8I_R40_PLL_AUDIO_REG 0x008 > + > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", > +"osc24M", 0x008, > +8, 7,/* N */ > +0, 5,/* M */ > +BIT(31), /* gate */ > +BIT(28), /* lock */ > +0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", > + "osc24
[PATCH v3 08/10] clk: sunxi-ng: support R40 SoC
Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng --- Changes in v3: - Rebased on current linux-next. Changes in v2: - Fixes according to the SoC's user manual. drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 + drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + include/dt-bindings/reset/sun8i-r40-ccu.h | 129 6 files changed, 1552 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 67acef3d2494..c11ad3375907 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -157,6 +157,16 @@ config SUN8I_DE2_CCU select SUNXI_CCU_DIV select SUNXI_CCU_GATE +config SUN8I_R40_CCU + bool "Support for the Allwinner R40 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP + default MACH_SUN8I + config SUN9I_A80_CCU bool "Support for the Allwinner A80 CCU" select SUNXI_CCU_DIV diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 0185c6ffadcb..217db667a994 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SUN8I_H3_CCU)+= ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o obj-$(CONFIG_SUN8I_DE2_CCU)+= ccu-sun8i-de2.o obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o +obj-$(CONFIG_SUN8I_R40_CCU)+= ccu-sun8i-r40.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c new file mode 100644 index ..484a8956f59c --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -0,0 +1,1153 @@ +/* + * Copyright (c) 2017 Icenowy Zheng + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun8i-r40.h" + +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", +"osc24M", 0x000, +8, 5, /* N */ +4, 2, /* K */ +0, 2, /* M */ +16, 2, /* P */ +BIT(31), /* gate */ +BIT(28), /* lock */ +0); + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN8I_R40_PLL_AUDIO_REG0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7,/* N */ + 0, 5,/* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", + "osc24M", 0x0010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24),/* frac enable */ + BIT(25),/* frac select */ + 27000, /* frac rate 0 */ + 29700, /*
