[RESEND PATCH v3 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller

2020-12-14 Thread Manish Narani 
Add documentation for Versal DWC3 controller. Add required property
'reg' for the same. Also add optional properties for snps,dwc3.

Signed-off-by: Manish Narani 
Reviewed-by: Rob Herring 
---
 .../devicetree/bindings/usb/dwc3-xilinx.txt | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt 
b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
index 4aae5b2cef56..0629f48cc807 100644
--- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
@@ -1,7 +1,8 @@
 Xilinx SuperSpeed DWC3 USB SoC controller
 
 Required properties:
-- compatible:  Should contain "xlnx,zynqmp-dwc3"
+- compatible:  May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
+- reg: Base address and length of the register control block
 - clocks:  A list of phandles for the clocks listed in clock-names
 - clock-names: Should contain the following:
   "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
@@ -13,12 +14,22 @@ Required child node:
 A child node must exist to represent the core DWC3 IP block. The name of
 the node is not important. The content of the node is defined in dwc3.txt.
 
+Optional properties for snps,dwc3:
+- dma-coherent:Enable this flag if CCI is enabled in design. Adding 
this
+   flag configures Global SoC bus Configuration Register and
+   Xilinx USB 3.0 IP - USB coherency register to enable CCI.
+- interrupt-names: Should contain the following:
+  "dwc_usb3"   USB gadget mode interrupts
+  "otg"USB OTG mode interrupts
+  "hiber"  USB hibernation interrupts
+
 Example device node:
 
usb@0 {
#address-cells = <0x2>;
#size-cells = <0x1>;
compatible = "xlnx,zynqmp-dwc3";
+   reg = <0x0 0xff9d 0x0 0x100>;
clock-names = "bus_clk" "ref_clk";
clocks = <&clk125>, <&clk125>;
ranges;
@@ -26,7 +37,9 @@ Example device node:
dwc3@fe20 {
compatible = "snps,dwc3";
reg = <0x0 0xfe20 0x4>;
-   interrupts = <0x0 0x41 0x4>;
+   interrupt-names = "dwc_usb3", "otg", "hiber";
+   interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
dr_mode = "host";
+   dma-coherent;
};
};
-- 
2.17.1

Re: [PATCH v3 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller

2020-10-13 Thread Rob Herring 
On Thu, 08 Oct 2020 18:36:55 +0530, Manish Narani wrote:
> Add documentation for Versal DWC3 controller. Add required property
> 'reg' for the same. Also add optional properties for snps,dwc3.
> 
> Signed-off-by: Manish Narani 
> ---
>  .../devicetree/bindings/usb/dwc3-xilinx.txt | 17 +++--
>  1 file changed, 15 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring

[PATCH v3 1/2] dt-bindings: usb: dwc3-xilinx: Add documentation for Versal DWC3 Controller

2020-10-08 Thread Manish Narani 
Add documentation for Versal DWC3 controller. Add required property
'reg' for the same. Also add optional properties for snps,dwc3.

Signed-off-by: Manish Narani 
---
 .../devicetree/bindings/usb/dwc3-xilinx.txt | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt 
b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
index 4aae5b2cef56..0629f48cc807 100644
--- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.txt
@@ -1,7 +1,8 @@
 Xilinx SuperSpeed DWC3 USB SoC controller
 
 Required properties:
-- compatible:  Should contain "xlnx,zynqmp-dwc3"
+- compatible:  May contain "xlnx,zynqmp-dwc3" or "xlnx,versal-dwc3"
+- reg: Base address and length of the register control block
 - clocks:  A list of phandles for the clocks listed in clock-names
 - clock-names: Should contain the following:
   "bus_clk" Master/Core clock, have to be >= 125 MHz for SS
@@ -13,12 +14,22 @@ Required child node:
 A child node must exist to represent the core DWC3 IP block. The name of
 the node is not important. The content of the node is defined in dwc3.txt.
 
+Optional properties for snps,dwc3:
+- dma-coherent:Enable this flag if CCI is enabled in design. Adding 
this
+   flag configures Global SoC bus Configuration Register and
+   Xilinx USB 3.0 IP - USB coherency register to enable CCI.
+- interrupt-names: Should contain the following:
+  "dwc_usb3"   USB gadget mode interrupts
+  "otg"USB OTG mode interrupts
+  "hiber"  USB hibernation interrupts
+
 Example device node:
 
usb@0 {
#address-cells = <0x2>;
#size-cells = <0x1>;
compatible = "xlnx,zynqmp-dwc3";
+   reg = <0x0 0xff9d 0x0 0x100>;
clock-names = "bus_clk" "ref_clk";
clocks = <&clk125>, <&clk125>;
ranges;
@@ -26,7 +37,9 @@ Example device node:
dwc3@fe20 {
compatible = "snps,dwc3";
reg = <0x0 0xfe20 0x4>;
-   interrupts = <0x0 0x41 0x4>;
+   interrupt-names = "dwc_usb3", "otg", "hiber";
+   interrupts = <0 65 4>, <0 69 4>, <0 75 4>;
dr_mode = "host";
+   dma-coherent;
};
};
-- 
2.17.1