Re: [PATCH v3 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings

2021-01-19 Thread Steen.Hegelund 
Hi Alex,

On Tue, 2021-01-19 at 21:35 +0100, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you
> know the content is safe
> 
> Hi,
> 
> Every patches need a commit message, even if in this case it will be
> very small.

Yes that is a mistake.  I will update the series.

> 
> On 14/01/2021 17:24:30+0100, Steen Hegelund wrote:
> > Signed-off-by: Steen Hegelund 
> > ---
> >  .../bindings/reset/microchip,rst.yaml | 59
> > +++
> >  1 file changed, 59 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/reset/microchip,rst.yaml
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/reset/microchip,rst.yaml
> > b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
> > new file mode 100644
> > index ..af01016e246f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
> > @@ -0,0 +1,59 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#;
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> > +
> > +title: Microchip Sparx5 Switch Reset Controller
> > +
> > +maintainers:
> > +  - Steen Hegelund 
> > +  - Lars Povlsen 
> > +
> > +description: |
> > +  The Microchip Sparx5 Switch provides reset control and
> > implements the following
> > +  functions
> > +    - One Time Switch Core Reset (Soft Reset)
> > +
> > +properties:
> > +  $nodename:
> > +    pattern: "^reset-controller@[0-9a-f]+$"
> > +
> > +  compatible:
> > +    const: microchip,sparx5-switch-reset
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  "#reset-cells":
> > +    const: 1
> > +
> > +  cpu-syscon:
> > +    $ref: "/schemas/types.yaml#/definitions/phandle"
> > +    description: syscon used to access CPU reset
> > +    maxItems: 1
> > +
> > +  gcb-syscon:
> > +    $ref: "/schemas/types.yaml#/definitions/phandle"
> > +    description: syscon used to access Global Control Block
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - "#reset-cells"
> > +  - cpu-syscon
> > +  - gcb-syscon
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    reset: reset-controller@0 {
> > +    compatible = "microchip,sparx5-switch-reset";
> > +    reg = <0x0 0x0>;
> > +    #reset-cells = <1>;
> > +    cpu-syscon = <_ctrl>;
> > +    gcb-syscon = <_ctrl>;
> > +    };
> > +
> > --
> > 2.29.2
> > 
> 
> --
> Alexandre Belloni, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com


Thanks for your comments
BR
Steen
-- 
BR
Steen

-=-=-=-=-=-=-=-=-=-=-=-=-=-=
steen.hegel...@microchip.com

Re: [PATCH v3 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings

2021-01-19 Thread Alexandre Belloni 
Hi,

Every patches need a commit message, even if in this case it will be
very small.

On 14/01/2021 17:24:30+0100, Steen Hegelund wrote:
> Signed-off-by: Steen Hegelund 
> ---
>  .../bindings/reset/microchip,rst.yaml | 59 +++
>  1 file changed, 59 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml 
> b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
> new file mode 100644
> index ..af01016e246f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#;
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> +
> +title: Microchip Sparx5 Switch Reset Controller
> +
> +maintainers:
> +  - Steen Hegelund 
> +  - Lars Povlsen 
> +
> +description: |
> +  The Microchip Sparx5 Switch provides reset control and implements the 
> following
> +  functions
> +- One Time Switch Core Reset (Soft Reset)
> +
> +properties:
> +  $nodename:
> +pattern: "^reset-controller@[0-9a-f]+$"
> +
> +  compatible:
> +const: microchip,sparx5-switch-reset
> +
> +  reg:
> +maxItems: 1
> +
> +  "#reset-cells":
> +const: 1
> +
> +  cpu-syscon:
> +$ref: "/schemas/types.yaml#/definitions/phandle"
> +description: syscon used to access CPU reset
> +maxItems: 1
> +
> +  gcb-syscon:
> +$ref: "/schemas/types.yaml#/definitions/phandle"
> +description: syscon used to access Global Control Block
> +maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - "#reset-cells"
> +  - cpu-syscon
> +  - gcb-syscon
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +reset: reset-controller@0 {
> +compatible = "microchip,sparx5-switch-reset";
> +reg = <0x0 0x0>;
> +#reset-cells = <1>;
> +cpu-syscon = <_ctrl>;
> +gcb-syscon = <_ctrl>;
> +};
> +
> -- 
> 2.29.2
> 

-- 
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[PATCH v3 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings

2021-01-14 Thread Steen Hegelund 
Signed-off-by: Steen Hegelund 
---
 .../bindings/reset/microchip,rst.yaml | 59 +++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml

diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml 
b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index ..af01016e246f
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+  - Steen Hegelund 
+  - Lars Povlsen 
+
+description: |
+  The Microchip Sparx5 Switch provides reset control and implements the 
following
+  functions
+- One Time Switch Core Reset (Soft Reset)
+
+properties:
+  $nodename:
+pattern: "^reset-controller@[0-9a-f]+$"
+
+  compatible:
+const: microchip,sparx5-switch-reset
+
+  reg:
+maxItems: 1
+
+  "#reset-cells":
+const: 1
+
+  cpu-syscon:
+$ref: "/schemas/types.yaml#/definitions/phandle"
+description: syscon used to access CPU reset
+maxItems: 1
+
+  gcb-syscon:
+$ref: "/schemas/types.yaml#/definitions/phandle"
+description: syscon used to access Global Control Block
+maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - "#reset-cells"
+  - cpu-syscon
+  - gcb-syscon
+
+additionalProperties: false
+
+examples:
+  - |
+reset: reset-controller@0 {
+compatible = "microchip,sparx5-switch-reset";
+reg = <0x0 0x0>;
+#reset-cells = <1>;
+cpu-syscon = <_ctrl>;
+gcb-syscon = <_ctrl>;
+};
+
-- 
2.29.2