Re: [PATCH v3 1/5] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema

[Rob Herring]

On Mon, 16 Nov 2020 17:24:23 +0100, Gregory CLEMENT wrote:
> Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
> Controller to YAML format
> 
> Signed-off-by: Gregory CLEMENT 
> ---
>  .../mscc,ocelot-icpu-intr.txt | 21 ---
>  .../mscc,ocelot-icpu-intr.yaml| 59 +++
>  2 files changed, 59 insertions(+), 21 deletions(-)
>  delete mode 100644 
> Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
>  create mode 100644 
> Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
> 


My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.example.dt.yaml:
 interrupt-controller@7070: '#address-cells' is a required property
From schema: 
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml


See https://patchwork.ozlabs.org/patch/1401029

The base for the patch is generally the last rc1. Any dependencies
should be noted.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

[PATCH v3 1/5] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema

[Gregory CLEMENT]

Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
Controller to YAML format

Signed-off-by: Gregory CLEMENT 
---
 .../mscc,ocelot-icpu-intr.txt | 21 ---
 .../mscc,ocelot-icpu-intr.yaml| 59 +++
 2 files changed, 59 insertions(+), 21 deletions(-)
 delete mode 100644 
Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
 create mode 100644 
Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml

diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
 
b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
deleted file mode 100644
index f5baeccb689f..
--- 
a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Microsemi Ocelot SoC ICPU Interrupt Controller
-
-Required properties:
-
-- compatible : should be "mscc,ocelot-icpu-intr"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
-  interrupt source. The value shall be 1.
-- interrupts : Specifies the CPU interrupt the controller is connected to.
-
-Example:
-
-   intc: interrupt-controller@7070 {
-   compatible = "mscc,ocelot-icpu-intr";
-   reg = <0x7070 0x70>;
-   #interrupt-cells = <1>;
-   interrupt-controller;
-   interrupt-parent = <>;
-   interrupts = <2>;
-   };
diff --git 
a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
 
b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
new file mode 100644
index ..3a537635a859
--- /dev/null
+++ 
b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: 
"http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Microsemi Ocelot SoC ICPU Interrupt Controller
+
+maintainers:
+  - Alexandre Belloni 
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+  the Microsemi Ocelot interrupt controller that is part of the
+  ICPU. It is connected directly to the MIPS core interrupt
+  controller.
+
+properties:
+  compatible:
+items:
+  - enum:
+  - mscc,ocelot-icpu-intr
+
+  '#interrupt-cells':
+const: 1
+
+  '#address-cells':
+const: 0
+
+  interrupt-controller: true
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+required:
+  - compatible
+  - '#interrupt-cells'
+  - '#address-cells'
+  - interrupt-controller
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+intc: interrupt-controller@7070 {
+compatible = "mscc,ocelot-icpu-intr";
+reg = <0x7070 0x70>;
+#interrupt-cells = <1>;
+interrupt-controller;
+interrupt-parent = <>;
+interrupts = <2>;
+};
+...
-- 
2.29.2