Re: [PATCH v3 10/12] spi: add driver for J-Core SPI controller

[Mark Brown]

On Thu, May 26, 2016 at 09:16:21PM -0400, Rich Felker wrote:

> Would you prefer I continue to submit this driver with new versions of
> the patch series, or separate it out for further review on its own?

It would be clearer to submit it separately.


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Re: [PATCH v3 10/12] spi: add driver for J-Core SPI controller

[Mark Brown]

On Thu, May 26, 2016 at 09:16:21PM -0400, Rich Felker wrote:

> Would you prefer I continue to submit this driver with new versions of
> the patch series, or separate it out for further review on its own?

It would be clearer to submit it separately.


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Re: [PATCH v3 10/12] spi: add driver for J-Core SPI controller

[Rich Felker]

On Wed, May 25, 2016 at 11:17:08AM +0100, Mark Brown wrote:
> On Wed, May 25, 2016 at 05:43:03AM +, Rich Felker wrote:
> 
> > changes based on ml discussion of the v2 patch. The chipselect change
> > has not been made yet, except for rewriting the current logic to be
> > more clear. If the decision is that it's needed, I can do it easily,
> > but it needs testing still.
> 
> You need to fix that, it's not good to just decide to ignore review
> comments.  It is astonishing that you are doing this while expecting to
> bypass the normal process for merging things.  I'm not going to look at
> this version, please ensure you have addressed all the feedback from the
> previous review before any new version you submit.

I've made and tested a change that looks like what you want, with the
hw->csReg's chipselect bits set initially high in the probe function,
and only the requested bit being modified by the chipselect function.
Would you prefer I continue to submit this driver with new versions of
the patch series, or separate it out for further review on its own?

Rich

Re: [PATCH v3 10/12] spi: add driver for J-Core SPI controller

[Rich Felker]

On Wed, May 25, 2016 at 11:17:08AM +0100, Mark Brown wrote:
> On Wed, May 25, 2016 at 05:43:03AM +, Rich Felker wrote:
> 
> > changes based on ml discussion of the v2 patch. The chipselect change
> > has not been made yet, except for rewriting the current logic to be
> > more clear. If the decision is that it's needed, I can do it easily,
> > but it needs testing still.
> 
> You need to fix that, it's not good to just decide to ignore review
> comments.  It is astonishing that you are doing this while expecting to
> bypass the normal process for merging things.  I'm not going to look at
> this version, please ensure you have addressed all the feedback from the
> previous review before any new version you submit.

I've made and tested a change that looks like what you want, with the
hw->csReg's chipselect bits set initially high in the probe function,
and only the requested bit being modified by the chipselect function.
Would you prefer I continue to submit this driver with new versions of
the patch series, or separate it out for further review on its own?

Rich

Re: [PATCH v3 10/12] spi: add driver for J-Core SPI controller

[Mark Brown]

On Wed, May 25, 2016 at 05:43:03AM +, Rich Felker wrote:

> changes based on ml discussion of the v2 patch. The chipselect change
> has not been made yet, except for rewriting the current logic to be
> more clear. If the decision is that it's needed, I can do it easily,
> but it needs testing still.

You need to fix that, it's not good to just decide to ignore review
comments.  It is astonishing that you are doing this while expecting to
bypass the normal process for merging things.  I'm not going to look at
this version, please ensure you have addressed all the feedback from the
previous review before any new version you submit.


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Re: [PATCH v3 10/12] spi: add driver for J-Core SPI controller

[Mark Brown]

On Wed, May 25, 2016 at 05:43:03AM +, Rich Felker wrote:

> changes based on ml discussion of the v2 patch. The chipselect change
> has not been made yet, except for rewriting the current logic to be
> more clear. If the decision is that it's needed, I can do it easily,
> but it needs testing still.

You need to fix that, it's not good to just decide to ignore review
comments.  It is astonishing that you are doing this while expecting to
bypass the normal process for merging things.  I'm not going to look at
this version, please ensure you have addressed all the feedback from the
previous review before any new version you submit.


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[PATCH v3 10/12] spi: add driver for J-Core SPI controller

[Rich Felker]

The J-Core "spi2" device is a PIO-based SPI master controller. It
differs from "bitbang" devices in that that it's clocked in hardware
rather than via soft clock modulation over gpio, and performs
byte-at-a-time transfers between the cpu and SPI controller.

This driver will be extended to support future versions of the J-Core
SPI controller with DMA transfers when they become available.

Signed-off-by: Rich Felker 
---

This version of the SPI patch eliminates USE_MESSAGE_MODE (the open
coding of transfer_one_message logic) and makes severl other minor
changes based on ml discussion of the v2 patch. The chipselect change
has not been made yet, except for rewriting the current logic to be
more clear. If the decision is that it's needed, I can do it easily,
but it needs testing still.

 drivers/spi/Kconfig |   4 +
 drivers/spi/Makefile|   1 +
 drivers/spi/spi-jcore.c | 209 
 3 files changed, 214 insertions(+)
 create mode 100644 drivers/spi/spi-jcore.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9d8c84b..5bd2ccf 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,10 @@ config SPI_IMX
  This enables using the Freescale i.MX SPI controllers in master
  mode.
 
+config SPI_JCORE
+   tristate "J-Core SPI Master"
+   depends on OF
+
 config SPI_LM70_LLP
tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
depends on PARPORT
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index fbb255c..6a34124 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
 obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
 obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
 obj-$(CONFIG_SPI_IMX)  += spi-imx.o
+obj-$(CONFIG_SPI_JCORE)+= spi-jcore.o
 obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
 obj-$(CONFIG_SPI_LP8841_RTC)   += spi-lp8841-rtc.o
 obj-$(CONFIG_SPI_MESON_SPIFC)  += spi-meson-spifc.o
diff --git a/drivers/spi/spi-jcore.c b/drivers/spi/spi-jcore.c
new file mode 100644
index 000..f239087
--- /dev/null
+++ b/drivers/spi/spi-jcore.c
@@ -0,0 +1,209 @@
+/*
+ * J-Core SPI controller driver
+ *
+ * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
+ *
+ * Current version by Rich Felker
+ * Based loosely on initial version by Oleksandr G Zhadan
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "jcore_spi"
+
+#define MAX_SPI_SPEED  1250/* 12.5 MHz */
+
+#define CTRL_REG   0x0
+#define DATA_REG   0x4
+
+#define SPI_NOCHIP_CS  0
+#define SPI_FLASH_CS   1
+#define SPI_CONF_CS2
+#define SPI_SD_CS  2
+#define SPI_CODEC_CS   3
+
+#define JCORE_SPI_CTRL_XMIT0x02
+#define JCORE_SPI_STAT_BUSY0x02
+#define JCORE_SPI_CTRL_LOOP0x08
+#define JCORE_SPI_CTRL_CS_BITS 0x15
+
+#define JCORE_SPI_WAIT_RDY_MAX_LOOP200
+
+struct jcore_spi {
+   struct spi_master *master;
+   void __iomem *base;
+   volatile unsigned int ctrlReg;
+   unsigned int csReg;
+   unsigned int speedReg;
+   unsigned int speed_hz;
+};
+
+static void jcore_spi_wait_till_ready(struct jcore_spi *hw, int timeout)
+{
+   while (timeout--) {
+   hw->ctrlReg = readl(hw->base + CTRL_REG);
+   if (!(hw->ctrlReg & JCORE_SPI_STAT_BUSY))
+   return;
+   cpu_relax();
+   }
+   dev_err(hw->master->dev.parent, "%s: Timeout..\n", __func__);
+}
+
+static void jcore_spi_program(struct jcore_spi *hw)
+{
+   jcore_spi_wait_till_ready(hw, JCORE_SPI_WAIT_RDY_MAX_LOOP);
+   writel(hw->csReg | hw->speedReg, hw->base + CTRL_REG);  
+}
+
+static void jcore_spi_chipsel(struct spi_device *spi, bool value)
+{
+   struct jcore_spi *hw = spi_master_get_devdata(spi->master);
+
+   dev_dbg(hw->master->dev.parent, "%s: CS=%d\n", __func__, value);
+
+   hw->csReg = JCORE_SPI_CTRL_CS_BITS ^ (!value << 2*spi->chip_select);
+
+   jcore_spi_program(hw);
+}
+
+static void jcore_spi_baudrate(struct jcore_spi *hw, int speed)
+{
+   if (speed == hw->speed_hz) return;
+   hw->speed_hz = speed;
+   hw->speedReg = ((MAX_SPI_SPEED / speed) - 1) << 27;
+   jcore_spi_program(hw);
+   dev_dbg(hw->master->dev.parent, "%s: speed=%d pre=0x%x\n",
+   __func__, speed, hw->speedReg);
+}
+
+static int jcore_spi_txrx(struct spi_master *master, struct spi_device *spi,
+ struct spi_transfer *t)
+{
+   struct jcore_spi *hw = spi_master_get_devdata(master);
+
+   void *ctrl_reg = hw->base + CTRL_REG;
+   void *data_reg = hw->base + DATA_REG;
+   unsigned int timeout;
+   u32 xmit;
+   u32 status;
+
+   /* data buffers */
+   const unsigned char *tx;
+

[PATCH v3 10/12] spi: add driver for J-Core SPI controller

[Rich Felker]

The J-Core "spi2" device is a PIO-based SPI master controller. It
differs from "bitbang" devices in that that it's clocked in hardware
rather than via soft clock modulation over gpio, and performs
byte-at-a-time transfers between the cpu and SPI controller.

This driver will be extended to support future versions of the J-Core
SPI controller with DMA transfers when they become available.

Signed-off-by: Rich Felker 
---

This version of the SPI patch eliminates USE_MESSAGE_MODE (the open
coding of transfer_one_message logic) and makes severl other minor
changes based on ml discussion of the v2 patch. The chipselect change
has not been made yet, except for rewriting the current logic to be
more clear. If the decision is that it's needed, I can do it easily,
but it needs testing still.

 drivers/spi/Kconfig |   4 +
 drivers/spi/Makefile|   1 +
 drivers/spi/spi-jcore.c | 209 
 3 files changed, 214 insertions(+)
 create mode 100644 drivers/spi/spi-jcore.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9d8c84b..5bd2ccf 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -285,6 +285,10 @@ config SPI_IMX
  This enables using the Freescale i.MX SPI controllers in master
  mode.
 
+config SPI_JCORE
+   tristate "J-Core SPI Master"
+   depends on OF
+
 config SPI_LM70_LLP
tristate "Parallel port adapter for LM70 eval board (DEVELOPMENT)"
depends on PARPORT
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index fbb255c..6a34124 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
 obj-$(CONFIG_SPI_GPIO) += spi-gpio.o
 obj-$(CONFIG_SPI_IMG_SPFI) += spi-img-spfi.o
 obj-$(CONFIG_SPI_IMX)  += spi-imx.o
+obj-$(CONFIG_SPI_JCORE)+= spi-jcore.o
 obj-$(CONFIG_SPI_LM70_LLP) += spi-lm70llp.o
 obj-$(CONFIG_SPI_LP8841_RTC)   += spi-lp8841-rtc.o
 obj-$(CONFIG_SPI_MESON_SPIFC)  += spi-meson-spifc.o
diff --git a/drivers/spi/spi-jcore.c b/drivers/spi/spi-jcore.c
new file mode 100644
index 000..f239087
--- /dev/null
+++ b/drivers/spi/spi-jcore.c
@@ -0,0 +1,209 @@
+/*
+ * J-Core SPI controller driver
+ *
+ * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
+ *
+ * Current version by Rich Felker
+ * Based loosely on initial version by Oleksandr G Zhadan
+ *
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "jcore_spi"
+
+#define MAX_SPI_SPEED  1250/* 12.5 MHz */
+
+#define CTRL_REG   0x0
+#define DATA_REG   0x4
+
+#define SPI_NOCHIP_CS  0
+#define SPI_FLASH_CS   1
+#define SPI_CONF_CS2
+#define SPI_SD_CS  2
+#define SPI_CODEC_CS   3
+
+#define JCORE_SPI_CTRL_XMIT0x02
+#define JCORE_SPI_STAT_BUSY0x02
+#define JCORE_SPI_CTRL_LOOP0x08
+#define JCORE_SPI_CTRL_CS_BITS 0x15
+
+#define JCORE_SPI_WAIT_RDY_MAX_LOOP200
+
+struct jcore_spi {
+   struct spi_master *master;
+   void __iomem *base;
+   volatile unsigned int ctrlReg;
+   unsigned int csReg;
+   unsigned int speedReg;
+   unsigned int speed_hz;
+};
+
+static void jcore_spi_wait_till_ready(struct jcore_spi *hw, int timeout)
+{
+   while (timeout--) {
+   hw->ctrlReg = readl(hw->base + CTRL_REG);
+   if (!(hw->ctrlReg & JCORE_SPI_STAT_BUSY))
+   return;
+   cpu_relax();
+   }
+   dev_err(hw->master->dev.parent, "%s: Timeout..\n", __func__);
+}
+
+static void jcore_spi_program(struct jcore_spi *hw)
+{
+   jcore_spi_wait_till_ready(hw, JCORE_SPI_WAIT_RDY_MAX_LOOP);
+   writel(hw->csReg | hw->speedReg, hw->base + CTRL_REG);  
+}
+
+static void jcore_spi_chipsel(struct spi_device *spi, bool value)
+{
+   struct jcore_spi *hw = spi_master_get_devdata(spi->master);
+
+   dev_dbg(hw->master->dev.parent, "%s: CS=%d\n", __func__, value);
+
+   hw->csReg = JCORE_SPI_CTRL_CS_BITS ^ (!value << 2*spi->chip_select);
+
+   jcore_spi_program(hw);
+}
+
+static void jcore_spi_baudrate(struct jcore_spi *hw, int speed)
+{
+   if (speed == hw->speed_hz) return;
+   hw->speed_hz = speed;
+   hw->speedReg = ((MAX_SPI_SPEED / speed) - 1) << 27;
+   jcore_spi_program(hw);
+   dev_dbg(hw->master->dev.parent, "%s: speed=%d pre=0x%x\n",
+   __func__, speed, hw->speedReg);
+}
+
+static int jcore_spi_txrx(struct spi_master *master, struct spi_device *spi,
+ struct spi_transfer *t)
+{
+   struct jcore_spi *hw = spi_master_get_devdata(master);
+
+   void *ctrl_reg = hw->base + CTRL_REG;
+   void *data_reg = hw->base + DATA_REG;
+   unsigned int timeout;
+   u32 xmit;
+   u32 status;
+
+   /* data buffers */
+   const unsigned char *tx;
+   unsigned char