[PATCH v3 10/34] misc: xlink-pcie: lh: Add PCIe EP DMA functionality
From: Srikanth Thokala Add Synopsys PCIe DWC core embedded-DMA functionality for local host Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Reviewed-by: Mark Gross Signed-off-by: Srikanth Thokala --- drivers/misc/xlink-pcie/local_host/Makefile | 1 + drivers/misc/xlink-pcie/local_host/dma.c| 575 drivers/misc/xlink-pcie/local_host/epf.c| 15 +- drivers/misc/xlink-pcie/local_host/epf.h| 41 ++ 4 files changed, 629 insertions(+), 3 deletions(-) create mode 100644 drivers/misc/xlink-pcie/local_host/dma.c diff --git a/drivers/misc/xlink-pcie/local_host/Makefile b/drivers/misc/xlink-pcie/local_host/Makefile index 514d3f0c91bc..54fc118e2dd1 100644 --- a/drivers/misc/xlink-pcie/local_host/Makefile +++ b/drivers/misc/xlink-pcie/local_host/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o mxlk_ep-objs := epf.o +mxlk_ep-objs += dma.o diff --git a/drivers/misc/xlink-pcie/local_host/dma.c b/drivers/misc/xlink-pcie/local_host/dma.c new file mode 100644 index ..42978fb0db49 --- /dev/null +++ b/drivers/misc/xlink-pcie/local_host/dma.c @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Keem Bay XLink PCIe Driver + * + * Copyright (C) 2021 Intel Corporation + */ +#include +#include +#include + +#include "epf.h" + +#define DMA_DBI_OFFSET (0x38) + +/* PCIe DMA control 1 register definitions. */ +#define DMA_CH_CONTROL1_CB_SHIFT (0) +#define DMA_CH_CONTROL1_TCB_SHIFT (1) +#define DMA_CH_CONTROL1_LLP_SHIFT (2) +#define DMA_CH_CONTROL1_LIE_SHIFT (3) +#define DMA_CH_CONTROL1_CS_SHIFT (5) +#define DMA_CH_CONTROL1_CCS_SHIFT (8) +#define DMA_CH_CONTROL1_LLE_SHIFT (9) +#define DMA_CH_CONTROL1_CB_MASK(BIT(DMA_CH_CONTROL1_CB_SHIFT)) +#define DMA_CH_CONTROL1_TCB_MASK (BIT(DMA_CH_CONTROL1_TCB_SHIFT)) +#define DMA_CH_CONTROL1_LLP_MASK (BIT(DMA_CH_CONTROL1_LLP_SHIFT)) +#define DMA_CH_CONTROL1_LIE_MASK (BIT(DMA_CH_CONTROL1_LIE_SHIFT)) +#define DMA_CH_CONTROL1_CS_MASK(0x3 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CCS_MASK (BIT(DMA_CH_CONTROL1_CCS_SHIFT)) +#define DMA_CH_CONTROL1_LLE_MASK (BIT(DMA_CH_CONTROL1_LLE_SHIFT)) + +/* DMA control 1 register Channel Status */ +#define DMA_CH_CONTROL1_CS_RUNNING (0x1 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CS_HALTED (0x2 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CS_STOPPED (0x3 << DMA_CH_CONTROL1_CS_SHIFT) + +/* PCIe DMA Engine enable register definitions. */ +#define DMA_ENGINE_EN_SHIFT(0) +#define DMA_ENGINE_EN_MASK (BIT(DMA_ENGINE_EN_SHIFT)) + +/* PCIe DMA interrupt registers definitions. */ +#define DMA_ABORT_INTERRUPT_SHIFT (16) +#define DMA_ABORT_INTERRUPT_MASK (0xFF << DMA_ABORT_INTERRUPT_SHIFT) +#define DMA_ABORT_INTERRUPT_CH_MASK(_c) (BIT(_c) << DMA_ABORT_INTERRUPT_SHIFT) +#define DMA_DONE_INTERRUPT_MASK(0xFF) +#define DMA_DONE_INTERRUPT_CH_MASK(_c) (BIT(_c)) +#define DMA_ALL_INTERRUPT_MASK \ + (DMA_ABORT_INTERRUPT_MASK | DMA_DONE_INTERRUPT_MASK) + +#define DMA_LL_ERROR_SHIFT (16) +#define DMA_CPL_ABORT_SHIFT(8) +#define DMA_CPL_TIMEOUT_SHIFT (16) +#define DMA_DATA_POI_SHIFT (24) +#define DMA_AR_ERROR_CH_MASK(_c) (BIT(_c)) +#define DMA_LL_ERROR_CH_MASK(_c) (BIT(_c) << DMA_LL_ERROR_SHIFT) +#define DMA_UNREQ_ERROR_CH_MASK(_c)(BIT(_c)) +#define DMA_CPL_ABORT_ERROR_CH_MASK(_c)(BIT(_c) << DMA_CPL_ABORT_SHIFT) +#define DMA_CPL_TIMEOUT_ERROR_CH_MASK(_c) (BIT(_c) << DMA_CPL_TIMEOUT_SHIFT) +#define DMA_DATA_POI_ERROR_CH_MASK(_c) (BIT(_c) << DMA_DATA_POI_SHIFT) + +#define DMA_LLLAIE_SHIFT (16) +#define DMA_LLLAIE_MASK(0xF << DMA_LLLAIE_SHIFT) + +#define DMA_CHAN_WRITE_MAX_WEIGHT (0x7) +#define DMA_CHAN_READ_MAX_WEIGHT (0x3) +#define DMA_CHAN0_WEIGHT_OFFSET(0) +#define DMA_CHAN1_WEIGHT_OFFSET(5) +#define DMA_CHAN2_WEIGHT_OFFSET(10) +#define DMA_CHAN3_WEIGHT_OFFSET(15) +#define DMA_CHAN_WRITE_ALL_MAX_WEIGHT \ + ((DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN0_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN1_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN2_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN3_WEIGHT_OFFSET)) +#define DMA_CHAN_READ_ALL_MAX_WEIGHT \ + ((DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN0_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN1_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN2_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN3_WEIGHT_OFFSET)) + +#define PCIE_REGS_PCIE_APP_CNTRL 0x8 +#define APP_XFER_PENDING BIT(6) +#define
[PATCH v3 10/34] misc: xlink-pcie: lh: Add PCIe EP DMA functionality
From: Srikanth Thokala Add Synopsys PCIe DWC core embedded-DMA functionality for local host Cc: Arnd Bergmann Cc: Greg Kroah-Hartman Reviewed-by: Mark Gross Signed-off-by: Srikanth Thokala --- drivers/misc/xlink-pcie/local_host/Makefile | 1 + drivers/misc/xlink-pcie/local_host/dma.c| 575 drivers/misc/xlink-pcie/local_host/epf.c| 15 +- drivers/misc/xlink-pcie/local_host/epf.h| 41 ++ 4 files changed, 629 insertions(+), 3 deletions(-) create mode 100644 drivers/misc/xlink-pcie/local_host/dma.c diff --git a/drivers/misc/xlink-pcie/local_host/Makefile b/drivers/misc/xlink-pcie/local_host/Makefile index 514d3f0c91bc..54fc118e2dd1 100644 --- a/drivers/misc/xlink-pcie/local_host/Makefile +++ b/drivers/misc/xlink-pcie/local_host/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_XLINK_PCIE_LH_DRIVER) += mxlk_ep.o mxlk_ep-objs := epf.o +mxlk_ep-objs += dma.o diff --git a/drivers/misc/xlink-pcie/local_host/dma.c b/drivers/misc/xlink-pcie/local_host/dma.c new file mode 100644 index ..42978fb0db49 --- /dev/null +++ b/drivers/misc/xlink-pcie/local_host/dma.c @@ -0,0 +1,575 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel Keem Bay XLink PCIe Driver + * + * Copyright (C) 2021 Intel Corporation + */ +#include +#include +#include + +#include "epf.h" + +#define DMA_DBI_OFFSET (0x38) + +/* PCIe DMA control 1 register definitions. */ +#define DMA_CH_CONTROL1_CB_SHIFT (0) +#define DMA_CH_CONTROL1_TCB_SHIFT (1) +#define DMA_CH_CONTROL1_LLP_SHIFT (2) +#define DMA_CH_CONTROL1_LIE_SHIFT (3) +#define DMA_CH_CONTROL1_CS_SHIFT (5) +#define DMA_CH_CONTROL1_CCS_SHIFT (8) +#define DMA_CH_CONTROL1_LLE_SHIFT (9) +#define DMA_CH_CONTROL1_CB_MASK(BIT(DMA_CH_CONTROL1_CB_SHIFT)) +#define DMA_CH_CONTROL1_TCB_MASK (BIT(DMA_CH_CONTROL1_TCB_SHIFT)) +#define DMA_CH_CONTROL1_LLP_MASK (BIT(DMA_CH_CONTROL1_LLP_SHIFT)) +#define DMA_CH_CONTROL1_LIE_MASK (BIT(DMA_CH_CONTROL1_LIE_SHIFT)) +#define DMA_CH_CONTROL1_CS_MASK(0x3 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CCS_MASK (BIT(DMA_CH_CONTROL1_CCS_SHIFT)) +#define DMA_CH_CONTROL1_LLE_MASK (BIT(DMA_CH_CONTROL1_LLE_SHIFT)) + +/* DMA control 1 register Channel Status */ +#define DMA_CH_CONTROL1_CS_RUNNING (0x1 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CS_HALTED (0x2 << DMA_CH_CONTROL1_CS_SHIFT) +#define DMA_CH_CONTROL1_CS_STOPPED (0x3 << DMA_CH_CONTROL1_CS_SHIFT) + +/* PCIe DMA Engine enable register definitions. */ +#define DMA_ENGINE_EN_SHIFT(0) +#define DMA_ENGINE_EN_MASK (BIT(DMA_ENGINE_EN_SHIFT)) + +/* PCIe DMA interrupt registers definitions. */ +#define DMA_ABORT_INTERRUPT_SHIFT (16) +#define DMA_ABORT_INTERRUPT_MASK (0xFF << DMA_ABORT_INTERRUPT_SHIFT) +#define DMA_ABORT_INTERRUPT_CH_MASK(_c) (BIT(_c) << DMA_ABORT_INTERRUPT_SHIFT) +#define DMA_DONE_INTERRUPT_MASK(0xFF) +#define DMA_DONE_INTERRUPT_CH_MASK(_c) (BIT(_c)) +#define DMA_ALL_INTERRUPT_MASK \ + (DMA_ABORT_INTERRUPT_MASK | DMA_DONE_INTERRUPT_MASK) + +#define DMA_LL_ERROR_SHIFT (16) +#define DMA_CPL_ABORT_SHIFT(8) +#define DMA_CPL_TIMEOUT_SHIFT (16) +#define DMA_DATA_POI_SHIFT (24) +#define DMA_AR_ERROR_CH_MASK(_c) (BIT(_c)) +#define DMA_LL_ERROR_CH_MASK(_c) (BIT(_c) << DMA_LL_ERROR_SHIFT) +#define DMA_UNREQ_ERROR_CH_MASK(_c)(BIT(_c)) +#define DMA_CPL_ABORT_ERROR_CH_MASK(_c)(BIT(_c) << DMA_CPL_ABORT_SHIFT) +#define DMA_CPL_TIMEOUT_ERROR_CH_MASK(_c) (BIT(_c) << DMA_CPL_TIMEOUT_SHIFT) +#define DMA_DATA_POI_ERROR_CH_MASK(_c) (BIT(_c) << DMA_DATA_POI_SHIFT) + +#define DMA_LLLAIE_SHIFT (16) +#define DMA_LLLAIE_MASK(0xF << DMA_LLLAIE_SHIFT) + +#define DMA_CHAN_WRITE_MAX_WEIGHT (0x7) +#define DMA_CHAN_READ_MAX_WEIGHT (0x3) +#define DMA_CHAN0_WEIGHT_OFFSET(0) +#define DMA_CHAN1_WEIGHT_OFFSET(5) +#define DMA_CHAN2_WEIGHT_OFFSET(10) +#define DMA_CHAN3_WEIGHT_OFFSET(15) +#define DMA_CHAN_WRITE_ALL_MAX_WEIGHT \ + ((DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN0_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN1_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN2_WEIGHT_OFFSET) | \ +(DMA_CHAN_WRITE_MAX_WEIGHT << DMA_CHAN3_WEIGHT_OFFSET)) +#define DMA_CHAN_READ_ALL_MAX_WEIGHT \ + ((DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN0_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN1_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN2_WEIGHT_OFFSET) |\ +(DMA_CHAN_READ_MAX_WEIGHT << DMA_CHAN3_WEIGHT_OFFSET)) + +#define PCIE_REGS_PCIE_APP_CNTRL 0x8 +#define APP_XFER_PENDING BIT(6) +#define
