Re: [PATCH v3 12/14] spi: mxic: patch for octal DTR mode support

[kbuild test robot]

Hi Mason,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on next-20200526]
[also build test WARNING on v5.7-rc7]
[cannot apply to spi/for-next xlnx/master linus/master linux/master v5.7-rc7 
v5.7-rc6 v5.7-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:
https://github.com/0day-ci/linux/commits/Mason-Yang/mtd-spi-nor-add-xSPI-Octal-DTR-support/20200528-162925
base:b0523c7b1c9d0edcd6c0fe6d2cb558a9ad5c60a8
config: x86_64-allyesconfig (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 
2d068e534f1671459e1b135852c1b3c10502e929)
reproduce (this is a W=1 build):
wget 
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot 

All warnings (new ones prefixed by >>, old ones prefixed by <<):

>> drivers/spi/spi-mxic.c:302:21: warning: result of comparison of constant 256 
>> with expression of type 'const u8' (aka 'const unsigned char') is always 
>> false [-Wtautological-constant-out-of-range-compare]
if (op->data.dtr == OP_DATA_DDR)
 ^  ~~~
1 warning generated.

vim +302 drivers/spi/spi-mxic.c

   282  
   283  static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op)
   284  {
   285  u32 cfg =  OP_CMD_BYTES(op->cmd.nbytes) |
   286 OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) |
   287 (op->cmd.dtr ? OP_CMD_DDR : 0);
   288  
   289  if (op->addr.nbytes)
   290  cfg |= OP_ADDR_BYTES(op->addr.nbytes) |
   291 OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) |
   292 (op->addr.dtr ? OP_ADDR_DDR : 0);
   293  
   294  if (op->dummy.nbytes)
   295  cfg |= OP_DUMMY_CYC(op->dummy.nbytes);
   296  
   297  if (op->data.nbytes) {
   298  cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) |
   299(op->data.dtr ? OP_DATA_DDR : 0);
   300  if (op->data.dir == SPI_MEM_DATA_IN) {
   301  cfg |= OP_READ;
 > 302  if (op->data.dtr == OP_DATA_DDR)
   303  cfg |= OP_DQS_EN;
   304  }
   305  }
   306  
   307  return cfg;
   308  }
   309  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org


.config.gz
Description: application/gzip

[PATCH v3 12/14] spi: mxic: patch for octal DTR mode support

[Mason Yang]

Driver patch for octal 8D-8D-8D mode support.

Signed-off-by: Mason Yang 
---
 drivers/spi/spi-mxic.c | 101 +
 1 file changed, 69 insertions(+), 32 deletions(-)

diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index 69491f3..c83c8c2 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -280,10 +280,58 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic)
   mxic->regs + HC_CFG);
 }
 
+static u32 mxic_spi_mem_prep_op_cfg(const struct spi_mem_op *op)
+{
+   u32 cfg =  OP_CMD_BYTES(op->cmd.nbytes) |
+  OP_CMD_BUSW(fls(op->cmd.buswidth) - 1) |
+  (op->cmd.dtr ? OP_CMD_DDR : 0);
+
+   if (op->addr.nbytes)
+   cfg |= OP_ADDR_BYTES(op->addr.nbytes) |
+  OP_ADDR_BUSW(fls(op->addr.buswidth) - 1) |
+  (op->addr.dtr ? OP_ADDR_DDR : 0);
+
+   if (op->dummy.nbytes)
+   cfg |= OP_DUMMY_CYC(op->dummy.nbytes);
+
+   if (op->data.nbytes) {
+   cfg |= OP_DATA_BUSW(fls(op->data.buswidth) - 1) |
+ (op->data.dtr ? OP_DATA_DDR : 0);
+   if (op->data.dir == SPI_MEM_DATA_IN) {
+   cfg |= OP_READ;
+   if (op->data.dtr == OP_DATA_DDR)
+   cfg |= OP_DQS_EN;
+   }
+   }
+
+   return cfg;
+}
+
+static void mxic_spi_set_hc_cfg(struct spi_device *spi, u32 flags)
+{
+   struct mxic_spi *mxic = spi_master_get_devdata(spi->master);
+   int nio = 1;
+
+   if (spi->mode & (SPI_RX_OCTAL | SPI_TX_OCTAL))
+   nio = 8;
+   else if (spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
+   nio = 4;
+   else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
+   nio = 2;
+
+   writel(flags | HC_CFG_NIO(nio) |
+  HC_CFG_TYPE(spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
+  HC_CFG_SLV_ACT(spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1),
+  mxic->regs + HC_CFG);
+}
+
 static int mxic_spi_data_xfer(struct mxic_spi *mxic, const void *txbuf,
  void *rxbuf, unsigned int len)
 {
unsigned int pos = 0;
+   bool dtr_enabled;
+
+   dtr_enabled = (readl(mxic->regs + SS_CTRL(0)) & OP_DATA_DDR);
 
while (pos < len) {
unsigned int nbytes = len - pos;
@@ -302,6 +350,9 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const 
void *txbuf,
if (ret)
return ret;
 
+   if (dtr_enabled && len & 0x1)
+   nbytes++;
+
writel(data, mxic->regs + TXD(nbytes % 4));
 
if (rxbuf) {
@@ -319,6 +370,8 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const 
void *txbuf,
 
data = readl(mxic->regs + RXD);
data >>= (8 * (4 - nbytes));
+   if (dtr_enabled && len & 0x1)
+   nbytes++;
memcpy(rxbuf + pos, , nbytes);
WARN_ON(readl(mxic->regs + INT_STS) & INT_RX_NOT_EMPTY);
} else {
@@ -335,8 +388,8 @@ static int mxic_spi_data_xfer(struct mxic_spi *mxic, const 
void *txbuf,
 static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
 const struct spi_mem_op *op)
 {
-   if (op->data.buswidth > 4 || op->addr.buswidth > 4 ||
-   op->dummy.buswidth > 4 || op->cmd.buswidth > 4)
+   if (op->data.buswidth > 8 || op->addr.buswidth > 8 ||
+   op->dummy.buswidth > 8 || op->cmd.buswidth > 8)
return false;
 
if (op->data.nbytes && op->dummy.nbytes &&
@@ -346,6 +399,9 @@ static bool mxic_spi_mem_supports_op(struct spi_mem *mem,
if (op->addr.nbytes > 7)
return false;
 
+   if (op->cmd.buswidth == 8 && op->cmd.nbytes == 2)
+   return true;
+
return spi_mem_default_supports_op(mem, op);
 }
 
@@ -353,47 +409,27 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
const struct spi_mem_op *op)
 {
struct mxic_spi *mxic = spi_master_get_devdata(mem->spi->master);
-   int nio = 1, i, ret;
-   u32 ss_ctrl;
-   u8 addr[8];
+   int i, ret;
+   u8 addr[8], cmd[2];
 
ret = mxic_spi_set_freq(mxic, mem->spi->max_speed_hz);
if (ret)
return ret;
 
-   if (mem->spi->mode & (SPI_TX_QUAD | SPI_RX_QUAD))
-   nio = 4;
-   else if (mem->spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
-   nio = 2;
+   mxic_spi_set_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN);
 
-   writel(HC_CFG_NIO(nio) |
-  HC_CFG_TYPE(mem->spi->chip_select, HC_CFG_TYPE_SPI_NOR) |
-  HC_CFG_SLV_ACT(mem->spi->chip_select) | HC_CFG_IDLE_SIO_LVL(1) |
-  HC_CFG_MAN_CS_EN,
-  mxic->regs + HC_CFG);
writel(HC_EN_BIT, mxic->regs + HC_EN);