Re: [PATCH v3 14/71] ARC: Low level IRQ/Trap/Exception Handling
Hi Al, On Thursday 24 January 2013 04:35 PM, Vineet Gupta wrote: > Signed-off-by: Vineet Gupta > Cc: Al Viro > --- > arch/arc/include/asm/entry.h | 495 > arch/arc/kernel/entry.S | 571 > ++ > 2 files changed, 1066 insertions(+), 0 deletions(-) > create mode 100644 arch/arc/include/asm/entry.h > create mode 100644 arch/arc/kernel/entry.S > > diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h > new file mode 100644 > index 000..63705b1 > --- /dev/null > +++ b/arch/arc/include/asm/entry.h > @@ -0,0 +1,495 @@ > +/* > + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + * Vineetg: Aug 28th 2008: Bug #94984 > + * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap > + * Normally CPU does this automatically, however when doing FAKE rtie, > + * we also need to explicitly do this. The problem in macros > + * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit > + * was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context > + * > + * Vineetg: May 5th 2008 > + * - Defined Stack Switching Macro to be reused in all intr/excp hdlrs > + * - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the > + * address Write back load ld.ab instead of seperate ld/add instn > + * > + * Amit Bhor, Sameer Dhavale: Codito Technologies 2004 > + */ > + > +#ifndef __ASM_ARC_ENTRY_H > +#define __ASM_ARC_ENTRY_H > + > +#ifdef __ASSEMBLY__ > +#include /* For NR_syscalls defination */ > +#include > +#include > +#include > +#include /* For THREAD_SIZE */ > + > +/* Note on the LD/ST addr modes with addr reg wback > + * > + * LD.a same as LD.aw > + * > + * LD.areg1, [reg2, x] => Pre Incr > + * Eff Addr for load = [reg2 + x] > + * > + * LD.ab reg1, [reg2, x] => Post Incr > + * Eff Addr for load = [reg2] > + */ > + > +/*-- > + * Save caller saved registers (scratch registers) ( r0 - r12 ) > + * Registers are pushed / popped in the order defined in struct ptregs > + * in asm/ptrace.h > + *-*/ > +.macro SAVE_CALLER_SAVED > + st.ar0, [sp, -4] > + st.ar1, [sp, -4] > + st.ar2, [sp, -4] > + st.ar3, [sp, -4] > + st.ar4, [sp, -4] > + st.ar5, [sp, -4] > + st.ar6, [sp, -4] > + st.ar7, [sp, -4] > + st.ar8, [sp, -4] > + st.ar9, [sp, -4] > + st.ar10, [sp, -4] > + st.ar11, [sp, -4] > + st.ar12, [sp, -4] > +.endm > + > +/*-- > + * Restore caller saved registers (scratch registers) > + *-*/ > +.macro RESTORE_CALLER_SAVED > + ld.ab r12, [sp, 4] > + ld.ab r11, [sp, 4] > + ld.ab r10, [sp, 4] > + ld.ab r9, [sp, 4] > + ld.ab r8, [sp, 4] > + ld.ab r7, [sp, 4] > + ld.ab r6, [sp, 4] > + ld.ab r5, [sp, 4] > + ld.ab r4, [sp, 4] > + ld.ab r3, [sp, 4] > + ld.ab r2, [sp, 4] > + ld.ab r1, [sp, 4] > + ld.ab r0, [sp, 4] > +.endm > + > + > +/*-- > + * Save callee saved registers (non scratch registers) ( r13 - r25 ) > + * on kernel stack. > + * User mode callee regs need to be saved in case of > + *-fork and friends for replicating from parent to child > + *-before going into do_signal( ) for ptrace/core-dump > + * Special case handling is required for r25 in case it is used by kernel > + * for caching task ptr. Low level exception/ISR save user mode r25 > + * into task->thread.user_r25. So it needs to be retrieved from there and > + * saved into kernel stack with rest of callee reg-file > + *-*/ > +.macro SAVE_CALLEE_SAVED_USER > + st.ar13, [sp, -4] > + st.ar14, [sp, -4] > + st.ar15, [sp, -4] > + st.ar16, [sp, -4] > + st.ar17, [sp, -4] > + st.ar18, [sp, -4] > + st.ar19, [sp, -4] > + st.ar20, [sp, -4] > + st.ar21, [sp, -4] > + st.ar22, [sp, -4] > + st.ar23, [sp, -4] > + st.ar24, [sp, -4] > + st.ar25, [sp, -4] > + > + /* move up by 1 word to "create" callee_regs->"stack_place_holder" */ > + sub sp, sp, 4 > +.endm > + > +/*-- > + * Save callee saved registers (non scratch registers) ( r13 - r25 ) > + * kernel mode callee regs needed to be saved in case of context switch > + * If r25 is used for caching task
Re: [PATCH v3 14/71] ARC: Low level IRQ/Trap/Exception Handling
Hi Al, On Thursday 24 January 2013 04:35 PM, Vineet Gupta wrote: Signed-off-by: Vineet Gupta vgu...@synopsys.com Cc: Al Viro v...@zeniv.linux.org.uk --- arch/arc/include/asm/entry.h | 495 arch/arc/kernel/entry.S | 571 ++ 2 files changed, 1066 insertions(+), 0 deletions(-) create mode 100644 arch/arc/include/asm/entry.h create mode 100644 arch/arc/kernel/entry.S diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h new file mode 100644 index 000..63705b1 --- /dev/null +++ b/arch/arc/include/asm/entry.h @@ -0,0 +1,495 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Vineetg: Aug 28th 2008: Bug #94984 + * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap + * Normally CPU does this automatically, however when doing FAKE rtie, + * we also need to explicitly do this. The problem in macros + * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit + * was being CLEARED rather then SET. Actually SET clears ZOL context + * + * Vineetg: May 5th 2008 + * - Defined Stack Switching Macro to be reused in all intr/excp hdlrs + * - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the + * address Write back load ld.ab instead of seperate ld/add instn + * + * Amit Bhor, Sameer Dhavale: Codito Technologies 2004 + */ + +#ifndef __ASM_ARC_ENTRY_H +#define __ASM_ARC_ENTRY_H + +#ifdef __ASSEMBLY__ +#include asm/unistd.h /* For NR_syscalls defination */ +#include asm/asm-offsets.h +#include asm/arcregs.h +#include asm/ptrace.h +#include asm/thread_info.h /* For THREAD_SIZE */ + +/* Note on the LD/ST addr modes with addr reg wback + * + * LD.a same as LD.aw + * + * LD.areg1, [reg2, x] = Pre Incr + * Eff Addr for load = [reg2 + x] + * + * LD.ab reg1, [reg2, x] = Post Incr + * Eff Addr for load = [reg2] + */ + +/*-- + * Save caller saved registers (scratch registers) ( r0 - r12 ) + * Registers are pushed / popped in the order defined in struct ptregs + * in asm/ptrace.h + *-*/ +.macro SAVE_CALLER_SAVED + st.ar0, [sp, -4] + st.ar1, [sp, -4] + st.ar2, [sp, -4] + st.ar3, [sp, -4] + st.ar4, [sp, -4] + st.ar5, [sp, -4] + st.ar6, [sp, -4] + st.ar7, [sp, -4] + st.ar8, [sp, -4] + st.ar9, [sp, -4] + st.ar10, [sp, -4] + st.ar11, [sp, -4] + st.ar12, [sp, -4] +.endm + +/*-- + * Restore caller saved registers (scratch registers) + *-*/ +.macro RESTORE_CALLER_SAVED + ld.ab r12, [sp, 4] + ld.ab r11, [sp, 4] + ld.ab r10, [sp, 4] + ld.ab r9, [sp, 4] + ld.ab r8, [sp, 4] + ld.ab r7, [sp, 4] + ld.ab r6, [sp, 4] + ld.ab r5, [sp, 4] + ld.ab r4, [sp, 4] + ld.ab r3, [sp, 4] + ld.ab r2, [sp, 4] + ld.ab r1, [sp, 4] + ld.ab r0, [sp, 4] +.endm + + +/*-- + * Save callee saved registers (non scratch registers) ( r13 - r25 ) + * on kernel stack. + * User mode callee regs need to be saved in case of + *-fork and friends for replicating from parent to child + *-before going into do_signal( ) for ptrace/core-dump + * Special case handling is required for r25 in case it is used by kernel + * for caching task ptr. Low level exception/ISR save user mode r25 + * into task-thread.user_r25. So it needs to be retrieved from there and + * saved into kernel stack with rest of callee reg-file + *-*/ +.macro SAVE_CALLEE_SAVED_USER + st.ar13, [sp, -4] + st.ar14, [sp, -4] + st.ar15, [sp, -4] + st.ar16, [sp, -4] + st.ar17, [sp, -4] + st.ar18, [sp, -4] + st.ar19, [sp, -4] + st.ar20, [sp, -4] + st.ar21, [sp, -4] + st.ar22, [sp, -4] + st.ar23, [sp, -4] + st.ar24, [sp, -4] + st.ar25, [sp, -4] + + /* move up by 1 word to create callee_regs-stack_place_holder */ + sub sp, sp, 4 +.endm + +/*-- + * Save callee saved registers (non scratch registers) ( r13 - r25 ) + * kernel mode callee regs needed to be saved in case of context switch + * If r25 is used for caching task pointer then that need not be
[PATCH v3 14/71] ARC: Low level IRQ/Trap/Exception Handling
Signed-off-by: Vineet Gupta Cc: Al Viro --- arch/arc/include/asm/entry.h | 495 arch/arc/kernel/entry.S | 571 ++ 2 files changed, 1066 insertions(+), 0 deletions(-) create mode 100644 arch/arc/include/asm/entry.h create mode 100644 arch/arc/kernel/entry.S diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h new file mode 100644 index 000..63705b1 --- /dev/null +++ b/arch/arc/include/asm/entry.h @@ -0,0 +1,495 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Vineetg: Aug 28th 2008: Bug #94984 + * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap + * Normally CPU does this automatically, however when doing FAKE rtie, + * we also need to explicitly do this. The problem in macros + * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit + * was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context + * + * Vineetg: May 5th 2008 + * - Defined Stack Switching Macro to be reused in all intr/excp hdlrs + * - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the + * address Write back load ld.ab instead of seperate ld/add instn + * + * Amit Bhor, Sameer Dhavale: Codito Technologies 2004 + */ + +#ifndef __ASM_ARC_ENTRY_H +#define __ASM_ARC_ENTRY_H + +#ifdef __ASSEMBLY__ +#include /* For NR_syscalls defination */ +#include +#include +#include +#include/* For THREAD_SIZE */ + +/* Note on the LD/ST addr modes with addr reg wback + * + * LD.a same as LD.aw + * + * LD.areg1, [reg2, x] => Pre Incr + * Eff Addr for load = [reg2 + x] + * + * LD.ab reg1, [reg2, x] => Post Incr + * Eff Addr for load = [reg2] + */ + +/*-- + * Save caller saved registers (scratch registers) ( r0 - r12 ) + * Registers are pushed / popped in the order defined in struct ptregs + * in asm/ptrace.h + *-*/ +.macro SAVE_CALLER_SAVED + st.ar0, [sp, -4] + st.ar1, [sp, -4] + st.ar2, [sp, -4] + st.ar3, [sp, -4] + st.ar4, [sp, -4] + st.ar5, [sp, -4] + st.ar6, [sp, -4] + st.ar7, [sp, -4] + st.ar8, [sp, -4] + st.ar9, [sp, -4] + st.ar10, [sp, -4] + st.ar11, [sp, -4] + st.ar12, [sp, -4] +.endm + +/*-- + * Restore caller saved registers (scratch registers) + *-*/ +.macro RESTORE_CALLER_SAVED + ld.ab r12, [sp, 4] + ld.ab r11, [sp, 4] + ld.ab r10, [sp, 4] + ld.ab r9, [sp, 4] + ld.ab r8, [sp, 4] + ld.ab r7, [sp, 4] + ld.ab r6, [sp, 4] + ld.ab r5, [sp, 4] + ld.ab r4, [sp, 4] + ld.ab r3, [sp, 4] + ld.ab r2, [sp, 4] + ld.ab r1, [sp, 4] + ld.ab r0, [sp, 4] +.endm + + +/*-- + * Save callee saved registers (non scratch registers) ( r13 - r25 ) + * on kernel stack. + * User mode callee regs need to be saved in case of + *-fork and friends for replicating from parent to child + *-before going into do_signal( ) for ptrace/core-dump + * Special case handling is required for r25 in case it is used by kernel + * for caching task ptr. Low level exception/ISR save user mode r25 + * into task->thread.user_r25. So it needs to be retrieved from there and + * saved into kernel stack with rest of callee reg-file + *-*/ +.macro SAVE_CALLEE_SAVED_USER + st.ar13, [sp, -4] + st.ar14, [sp, -4] + st.ar15, [sp, -4] + st.ar16, [sp, -4] + st.ar17, [sp, -4] + st.ar18, [sp, -4] + st.ar19, [sp, -4] + st.ar20, [sp, -4] + st.ar21, [sp, -4] + st.ar22, [sp, -4] + st.ar23, [sp, -4] + st.ar24, [sp, -4] + st.ar25, [sp, -4] + + /* move up by 1 word to "create" callee_regs->"stack_place_holder" */ + sub sp, sp, 4 +.endm + +/*-- + * Save callee saved registers (non scratch registers) ( r13 - r25 ) + * kernel mode callee regs needed to be saved in case of context switch + * If r25 is used for caching task pointer then that need not be saved + * as it can be re-created from current task global + *-*/ +.macro SAVE_CALLEE_SAVED_KERNEL + st.ar13, [sp, -4] + st.ar14, [sp, -4]
[PATCH v3 14/71] ARC: Low level IRQ/Trap/Exception Handling
Signed-off-by: Vineet Gupta vgu...@synopsys.com Cc: Al Viro v...@zeniv.linux.org.uk --- arch/arc/include/asm/entry.h | 495 arch/arc/kernel/entry.S | 571 ++ 2 files changed, 1066 insertions(+), 0 deletions(-) create mode 100644 arch/arc/include/asm/entry.h create mode 100644 arch/arc/kernel/entry.S diff --git a/arch/arc/include/asm/entry.h b/arch/arc/include/asm/entry.h new file mode 100644 index 000..63705b1 --- /dev/null +++ b/arch/arc/include/asm/entry.h @@ -0,0 +1,495 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Vineetg: Aug 28th 2008: Bug #94984 + * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap + * Normally CPU does this automatically, however when doing FAKE rtie, + * we also need to explicitly do this. The problem in macros + * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit + * was being CLEARED rather then SET. Actually SET clears ZOL context + * + * Vineetg: May 5th 2008 + * - Defined Stack Switching Macro to be reused in all intr/excp hdlrs + * - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the + * address Write back load ld.ab instead of seperate ld/add instn + * + * Amit Bhor, Sameer Dhavale: Codito Technologies 2004 + */ + +#ifndef __ASM_ARC_ENTRY_H +#define __ASM_ARC_ENTRY_H + +#ifdef __ASSEMBLY__ +#include asm/unistd.h/* For NR_syscalls defination */ +#include asm/asm-offsets.h +#include asm/arcregs.h +#include asm/ptrace.h +#include asm/thread_info.h /* For THREAD_SIZE */ + +/* Note on the LD/ST addr modes with addr reg wback + * + * LD.a same as LD.aw + * + * LD.areg1, [reg2, x] = Pre Incr + * Eff Addr for load = [reg2 + x] + * + * LD.ab reg1, [reg2, x] = Post Incr + * Eff Addr for load = [reg2] + */ + +/*-- + * Save caller saved registers (scratch registers) ( r0 - r12 ) + * Registers are pushed / popped in the order defined in struct ptregs + * in asm/ptrace.h + *-*/ +.macro SAVE_CALLER_SAVED + st.ar0, [sp, -4] + st.ar1, [sp, -4] + st.ar2, [sp, -4] + st.ar3, [sp, -4] + st.ar4, [sp, -4] + st.ar5, [sp, -4] + st.ar6, [sp, -4] + st.ar7, [sp, -4] + st.ar8, [sp, -4] + st.ar9, [sp, -4] + st.ar10, [sp, -4] + st.ar11, [sp, -4] + st.ar12, [sp, -4] +.endm + +/*-- + * Restore caller saved registers (scratch registers) + *-*/ +.macro RESTORE_CALLER_SAVED + ld.ab r12, [sp, 4] + ld.ab r11, [sp, 4] + ld.ab r10, [sp, 4] + ld.ab r9, [sp, 4] + ld.ab r8, [sp, 4] + ld.ab r7, [sp, 4] + ld.ab r6, [sp, 4] + ld.ab r5, [sp, 4] + ld.ab r4, [sp, 4] + ld.ab r3, [sp, 4] + ld.ab r2, [sp, 4] + ld.ab r1, [sp, 4] + ld.ab r0, [sp, 4] +.endm + + +/*-- + * Save callee saved registers (non scratch registers) ( r13 - r25 ) + * on kernel stack. + * User mode callee regs need to be saved in case of + *-fork and friends for replicating from parent to child + *-before going into do_signal( ) for ptrace/core-dump + * Special case handling is required for r25 in case it is used by kernel + * for caching task ptr. Low level exception/ISR save user mode r25 + * into task-thread.user_r25. So it needs to be retrieved from there and + * saved into kernel stack with rest of callee reg-file + *-*/ +.macro SAVE_CALLEE_SAVED_USER + st.ar13, [sp, -4] + st.ar14, [sp, -4] + st.ar15, [sp, -4] + st.ar16, [sp, -4] + st.ar17, [sp, -4] + st.ar18, [sp, -4] + st.ar19, [sp, -4] + st.ar20, [sp, -4] + st.ar21, [sp, -4] + st.ar22, [sp, -4] + st.ar23, [sp, -4] + st.ar24, [sp, -4] + st.ar25, [sp, -4] + + /* move up by 1 word to create callee_regs-stack_place_holder */ + sub sp, sp, 4 +.endm + +/*-- + * Save callee saved registers (non scratch registers) ( r13 - r25 ) + * kernel mode callee regs needed to be saved in case of context switch + * If r25 is used for caching task pointer then that need not be saved + * as it can be re-created from current task global +
