Re: [PATCH v3 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board

2021-02-22 Thread Michael Walle

Am 2021-02-22 22:26, schrieb Heiko Thiery:

The Kontron pitx-imx8m board is based on an i.MX8MQ soc.

Signed-off-by: Heiko Thiery 
Reviewed-by: Krzysztof Kozlowski 


Reviewed-by: Michael Walle 


[PATCH v3 2/2] arm64: dts: fsl: add support for Kontron pitx-imx8m board

2021-02-22 Thread Heiko Thiery
The Kontron pitx-imx8m board is based on an i.MX8MQ soc.

Signed-off-by: Heiko Thiery 
Reviewed-by: Krzysztof Kozlowski 
---
v2:
 - bring root nodes in alphabetical order
 - remove pinctrl_gpio_keys for pciewake
 - remove pinctrl_sai2 and pinctrl_spdfif1 since it is not used yet

 Thanks to Michael Walle:
 - add pinctrl for regulator-v-3v3-sd
 - add name for regulator swbst
 - add comment about currently unused audio codec
 - put usb_phy entry in correct alphabetical order

 Thanks to Krzysztof Kozlowski:
 - use generic names for pcie-refclk, tpm, fan-controller, sensor
 - remove empty line
 - fix group name to match schema (ecspi2cs -> ecspi2csgrp)

v3:
 Thanks to Michael Walle:
 - set compatible as first in regulator-v-3v3-sd node
 - remove audio-codec@1a node

 Thanks to Krzysztof Kozlowski:
 - use more generic name for pcie reference clock

 arch/arm64/boot/dts/freescale/Makefile|   1 +
 .../freescale/imx8mq-kontron-pitx-imx8m.dts   | 632 ++
 2 files changed, 633 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile 
b/arch/arm64/boot/dts/freescale/Makefile
index 6438db3822f8..9fc2c6f64407 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r2.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-r3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts 
b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
new file mode 100644
index ..2069f8439b40
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree File for the Kontron pitx-imx8m board.
+ *
+ * Copyright (C) 2021 Heiko Thiery 
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include 
+
+/ {
+   model = "Kontron pITX-imx8m";
+   compatible = "kontron,pitx-imx8m", "fsl,imx8mq";
+
+   aliases {
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   mmc0 = 
+   mmc1 = 
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   spi0 = 
+   spi1 = 
+   };
+
+   chosen {
+   stdout-path = "serial2:115200n8";
+   };
+
+   pcie0_refclk: pcie0-clock {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <1>;
+   };
+
+   pcie1_refclk: pcie1-clock {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <1>;
+   };
+
+   reg_usdhc2_vmmc: regulator-v-3v3-sd {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <_reg_usdhc2>;
+   regulator-name = "V_3V3_SD";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = < 19 GPIO_ACTIVE_HIGH>;
+   off-on-delay-us = <2>;
+   enable-active-high;
+   };
+
+   tpm_reset: tpm-reset {
+   compatible = "gpio-reset";
+   reset-gpios = < 2 GPIO_ACTIVE_LOW>;
+   reset-delay-us = <2>;
+   reset-post-delay-ms = <60>;
+   #reset-cells = <0>;
+   };
+
+   usb_hub_reset: usb-hub-reset {
+   compatible = "gpio-reset";
+   reset-gpios = < 4 GPIO_ACTIVE_LOW>;
+   reset-delay-us = <3000>;
+   reset-post-delay-ms = <50>;
+   #reset-cells = <0>;
+   };
+};
+
+ {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_ecspi2 _ecspi2_cs>;
+   cs-gpios = < 13 GPIO_ACTIVE_LOW>;
+   status = "okay";
+
+   tpm@0 {
+   compatible = "infineon,slb9670";
+   reg = <0>;
+   resets = <_reset>;
+   spi-max-frequency = <4300>;
+   };
+};
+
+ {
+   pinctrl-names = "default";
+   pinctrl-0 = <_fec1>;
+   phy-mode = "rgmii-id";
+   phy-handle = <>;
+   phy-reset-gpios = < 11 GPIO_ACTIVE_LOW>;
+   fsl,magic-packet;
+   status = "okay";
+
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ethphy0: ethernet-phy@0 {
+   compatible = "ethernet-phy-ieee802.3-c22";
+   reg = <0>;
+   ti,rx-internal-delay = ;
+