Re: [PATCH v3 2/2] clk: qcom: Add lpass clock controller driver for SDM845
On 9/6/2018 7:21 AM, Stephen Boyd wrote: Quoting Taniya Das (2018-09-05 11:26:10) On 8/28/2018 2:41 AM, Stephen Boyd wrote: Quoting Taniya Das (2018-08-03 05:21:14) diff --git a/drivers/clk/qcom/lpasscc-sdm845.c b/drivers/clk/qcom/lpasscc-sdm845.c new file mode 100644 index 000..6f387f9 --- /dev/null +++ b/drivers/clk/qcom/lpasscc-sdm845.c [...] + +/* CLK_OFF would not toggle until LPASS is not out of reset */ Can we change the branch ops to check for out of reset or not? Do the clks even work when LPASS isn't out of reset? Why would the clk APIs even be called on here if it hadn't taken LPASS out of reset? The branches need to be turned ON before the LPASS is out of reset. But we would not be able to check the CLK_ENABLE bit. Ok. Are the branches actually outputting any clk frequency when LPASS is in reset? It sounds like the hardware is broken and we can't ever check the halt bits? Yes, they would output when the reset is pulled for LPASS. These are as per the steps to be followed to bring the LPASS out of reset. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
Re: [PATCH v3 2/2] clk: qcom: Add lpass clock controller driver for SDM845
Quoting Taniya Das (2018-09-05 11:26:10) > On 8/28/2018 2:41 AM, Stephen Boyd wrote: > > Quoting Taniya Das (2018-08-03 05:21:14) > >> diff --git a/drivers/clk/qcom/lpasscc-sdm845.c > >> b/drivers/clk/qcom/lpasscc-sdm845.c > >> new file mode 100644 > >> index 000..6f387f9 > >> --- /dev/null > >> +++ b/drivers/clk/qcom/lpasscc-sdm845.c > > [...] > >> + > >> +/* CLK_OFF would not toggle until LPASS is not out of reset */ > > > > Can we change the branch ops to check for out of reset or not? Do the > > clks even work when LPASS isn't out of reset? Why would the clk APIs > > even be called on here if it hadn't taken LPASS out of reset? > > > > The branches need to be turned ON before the LPASS is out of reset. > But we would not be able to check the CLK_ENABLE bit. Ok. Are the branches actually outputting any clk frequency when LPASS is in reset? It sounds like the hardware is broken and we can't ever check the halt bits?
Re: [PATCH v3 2/2] clk: qcom: Add lpass clock controller driver for SDM845
Hello Stephen,
Thanks for the review comments.
On 8/28/2018 2:41 AM, Stephen Boyd wrote:
Quoting Taniya Das (2018-08-03 05:21:14)
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 2b69cf2..7bd940d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -254,6 +254,15 @@ config SDM_VIDEOCC_845
Say Y if you want to support video devices and functionality such as
video encode and decode.
+config SDM_LPASSCC_845
+ tristate "SDM845 LPASS Clock Controller"
Spell out the acronym? So "SDM845 Low Power Audio Subsystem (LPASS)
Clock Controller"?
Sure will update in the next patch.
+ depends on COMMON_CLK_QCOM
+ select SDM_GCC_845
+ help
+ Support for the LPASS clock controller on SDM845 devices.
+ Say Y if you want to use the LPASS branch clocks of the LPASS clock
+ controller to reset the LPASS subsystem.
+
config SPMI_PMIC_CLKDIV
tristate "SPMI PMIC clkdiv Support"
depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 0f694ed..068cf53 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3086,6 +3086,32 @@ enum {
},
};
+static struct clk_branch gcc_lpass_q6_axi_clk = {
+ .halt_reg = 0x47000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x47000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_lpass_q6_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_lpass_sway_clk = {
+ .halt_reg = 0x47008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x47008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_lpass_sway_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
@@ -3383,6 +3409,8 @@ enum {
[GPLL4] = &gpll4.clkr,
[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
+ [GCC_LPASS_Q6_AXI_CLK] = NULL,
+ [GCC_LPASS_SWAY_CLK] = NULL,
};
static const struct qcom_reset_map gcc_sdm845_resets[] = {
diff --git a/drivers/clk/qcom/lpasscc-sdm845.c
b/drivers/clk/qcom/lpasscc-sdm845.c
new file mode 100644
index 000..6f387f9
--- /dev/null
+++ b/drivers/clk/qcom/lpasscc-sdm845.c
[...]
+
+/* CLK_OFF would not toggle until LPASS is not out of reset */
Can we change the branch ops to check for out of reset or not? Do the
clks even work when LPASS isn't out of reset? Why would the clk APIs
even be called on here if it hadn't taken LPASS out of reset?
The branches need to be turned ON before the LPASS is out of reset.
But we would not be able to check the CLK_ENABLE bit.
+static struct clk_branch lpass_qdsp6ss_sleep_clk = {
+ .halt_reg = 0x3c,
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x3c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "lpass_qdsp6ss_sleep_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct regmap_config lpass_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .fast_io= true,
+};
+
+static struct clk_regmap *lpass_cc_sdm845_clocks[] = {
+ [LPASS_AUDIO_WRAPPER_AON_CLK] = &lpass_audio_wrapper_aon_clk.clkr,
+ [LPASS_Q6SS_AHBM_AON_CLK] = &lpass_q6ss_ahbm_aon_clk.clkr,
+ [LPASS_Q6SS_AHBS_AON_CLK] = &lpass_q6ss_ahbs_aon_clk.clkr,
+};
+
+static const struct qcom_cc_desc lpass_cc_sdm845_desc = {
+ .config = &lpass_regmap_config,
+ .clks = lpass_cc_sdm845_clocks,
+ .num_clks = ARRAY_SIZE(lpass_cc_sdm845_clocks),
+};
+
+static struct clk_regmap *lpass_qdsp6ss_sdm845_clocks[] = {
+ [LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
+ [LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
+ [LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
+};
+
+static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = {
+ .config = &lpass_regmap_config,
+ .clks = lpass_qdsp6ss_sdm845_clocks,
+ .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks),
+};
+
+static int lpass_clocks_sdm845_probe(struct platform_device *pdev, int index,
+const struct qcom_cc_desc *desc)
+{
+ struct regmap *regmap;
+ struct resource *res;
+ void __iomem *base;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, index);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (I
Re: [PATCH v3 2/2] clk: qcom: Add lpass clock controller driver for SDM845
Quoting Taniya Das (2018-08-03 05:21:14)
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 2b69cf2..7bd940d 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -254,6 +254,15 @@ config SDM_VIDEOCC_845
> Say Y if you want to support video devices and functionality such as
> video encode and decode.
>
> +config SDM_LPASSCC_845
> + tristate "SDM845 LPASS Clock Controller"
Spell out the acronym? So "SDM845 Low Power Audio Subsystem (LPASS)
Clock Controller"?
> + depends on COMMON_CLK_QCOM
> + select SDM_GCC_845
> + help
> + Support for the LPASS clock controller on SDM845 devices.
> + Say Y if you want to use the LPASS branch clocks of the LPASS clock
> + controller to reset the LPASS subsystem.
> +
> config SPMI_PMIC_CLKDIV
> tristate "SPMI PMIC clkdiv Support"
> depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
> diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
> index 0f694ed..068cf53 100644
> --- a/drivers/clk/qcom/gcc-sdm845.c
> +++ b/drivers/clk/qcom/gcc-sdm845.c
> @@ -3086,6 +3086,32 @@ enum {
> },
> };
>
> +static struct clk_branch gcc_lpass_q6_axi_clk = {
> + .halt_reg = 0x47000,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x47000,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_lpass_q6_axi_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch gcc_lpass_sway_clk = {
> + .halt_reg = 0x47008,
> + .halt_check = BRANCH_HALT,
> + .clkr = {
> + .enable_reg = 0x47008,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_lpass_sway_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> static struct gdsc pcie_0_gdsc = {
> .gdscr = 0x6b004,
> .pd = {
> @@ -3383,6 +3409,8 @@ enum {
> [GPLL4] = &gpll4.clkr,
> [GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
> [GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
> + [GCC_LPASS_Q6_AXI_CLK] = NULL,
> + [GCC_LPASS_SWAY_CLK] = NULL,
> };
>
> static const struct qcom_reset_map gcc_sdm845_resets[] = {
> diff --git a/drivers/clk/qcom/lpasscc-sdm845.c
> b/drivers/clk/qcom/lpasscc-sdm845.c
> new file mode 100644
> index 000..6f387f9
> --- /dev/null
> +++ b/drivers/clk/qcom/lpasscc-sdm845.c
[...]
> +
> +/* CLK_OFF would not toggle until LPASS is not out of reset */
Can we change the branch ops to check for out of reset or not? Do the
clks even work when LPASS isn't out of reset? Why would the clk APIs
even be called on here if it hadn't taken LPASS out of reset?
> +static struct clk_branch lpass_qdsp6ss_sleep_clk = {
> + .halt_reg = 0x3c,
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x3c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "lpass_qdsp6ss_sleep_clk",
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static struct regmap_config lpass_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .fast_io= true,
> +};
> +
> +static struct clk_regmap *lpass_cc_sdm845_clocks[] = {
> + [LPASS_AUDIO_WRAPPER_AON_CLK] = &lpass_audio_wrapper_aon_clk.clkr,
> + [LPASS_Q6SS_AHBM_AON_CLK] = &lpass_q6ss_ahbm_aon_clk.clkr,
> + [LPASS_Q6SS_AHBS_AON_CLK] = &lpass_q6ss_ahbs_aon_clk.clkr,
> +};
> +
> +static const struct qcom_cc_desc lpass_cc_sdm845_desc = {
> + .config = &lpass_regmap_config,
> + .clks = lpass_cc_sdm845_clocks,
> + .num_clks = ARRAY_SIZE(lpass_cc_sdm845_clocks),
> +};
> +
> +static struct clk_regmap *lpass_qdsp6ss_sdm845_clocks[] = {
> + [LPASS_QDSP6SS_XO_CLK] = &lpass_qdsp6ss_xo_clk.clkr,
> + [LPASS_QDSP6SS_SLEEP_CLK] = &lpass_qdsp6ss_sleep_clk.clkr,
> + [LPASS_QDSP6SS_CORE_CLK] = &lpass_qdsp6ss_core_clk.clkr,
> +};
> +
> +static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = {
> + .config = &lpass_regmap_config,
> + .clks = lpass_qdsp6ss_sdm845_clocks,
> + .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks),
> +};
> +
> +static int lpass_clocks_sdm845_probe(struct platform_device *pdev, int index,
> +const struct qcom_cc_desc *desc)
> +{
> + struct regmap *regmap;
> + struct resource *res;
> + void __iomem *base;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, index);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> +
[PATCH v3 2/2] clk: qcom: Add lpass clock controller driver for SDM845
Add support for the lpass clock controller found on SDM845 based devices.
This would allow lpass peripheral loader drivers to control the clocks to
bring the subsystem out of reset.
LPASS clocks present on the global clock controller would be registered
with the clock framework based on the device tree flag.
Signed-off-by: Taniya Das
---
drivers/clk/qcom/Kconfig | 9 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/gcc-sdm845.c | 35 +++
drivers/clk/qcom/lpasscc-sdm845.c | 189 ++
4 files changed, 234 insertions(+)
create mode 100644 drivers/clk/qcom/lpasscc-sdm845.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 2b69cf2..7bd940d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -254,6 +254,15 @@ config SDM_VIDEOCC_845
Say Y if you want to support video devices and functionality such as
video encode and decode.
+config SDM_LPASSCC_845
+ tristate "SDM845 LPASS Clock Controller"
+ depends on COMMON_CLK_QCOM
+ select SDM_GCC_845
+ help
+ Support for the LPASS clock controller on SDM845 devices.
+ Say Y if you want to use the LPASS branch clocks of the LPASS clock
+ controller to reset the LPASS subsystem.
+
config SPMI_PMIC_CLKDIV
tristate "SPMI PMIC clkdiv Support"
depends on (COMMON_CLK_QCOM && SPMI) || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 599ab91..df2bd1f 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -40,5 +40,6 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
+obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index 0f694ed..068cf53 100644
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -3086,6 +3086,32 @@ enum {
},
};
+static struct clk_branch gcc_lpass_q6_axi_clk = {
+ .halt_reg = 0x47000,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x47000,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_lpass_q6_axi_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch gcc_lpass_sway_clk = {
+ .halt_reg = 0x47008,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0x47008,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_lpass_sway_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct gdsc pcie_0_gdsc = {
.gdscr = 0x6b004,
.pd = {
@@ -3383,6 +3409,8 @@ enum {
[GPLL4] = &gpll4.clkr,
[GCC_CPUSS_DVM_BUS_CLK] = &gcc_cpuss_dvm_bus_clk.clkr,
[GCC_CPUSS_GNOC_CLK] = &gcc_cpuss_gnoc_clk.clkr,
+ [GCC_LPASS_Q6_AXI_CLK] = NULL,
+ [GCC_LPASS_SWAY_CLK] = NULL,
};
static const struct qcom_reset_map gcc_sdm845_resets[] = {
@@ -3472,6 +3500,13 @@ static int gcc_sdm845_probe(struct platform_device *pdev)
regmap_update_bits(regmap, 0x09ffc, 0x3, 0x3);
regmap_update_bits(regmap, 0x71028, 0x3, 0x3);
+ if (of_property_read_bool(pdev->dev.of_node, "qcom,lpass-protected")) {
+ gcc_sdm845_clocks[GCC_LPASS_Q6_AXI_CLK] =
+ &gcc_lpass_q6_axi_clk.clkr;
+ gcc_sdm845_clocks[GCC_LPASS_SWAY_CLK] =
+ &gcc_lpass_sway_clk.clkr;
+ }
+
return qcom_cc_really_probe(pdev, &gcc_sdm845_desc, regmap);
}
diff --git a/drivers/clk/qcom/lpasscc-sdm845.c
b/drivers/clk/qcom/lpasscc-sdm845.c
new file mode 100644
index 000..6f387f9
--- /dev/null
+++ b/drivers/clk/qcom/lpasscc-sdm845.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-regmap.h"
+#include "clk-branch.h"
+#include "common.h"
+
+static struct clk_branch lpass_audio_wrapper_aon_clk = {
+ .halt_reg = 0x098,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_reg = 0x098,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "lpass_audio_wrapper_aon_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch lpass_q6ss_ahbm_aon_clk = {
+ .halt_reg = 0x12000,
+ .halt_check = BRANCH_VOTED,
+ .clkr = {
+ .enable_re
