Re: [PATCH v3 2/4] arm64: dts: qcom: msm8976: Add MDSS nodes

[Konrad Dybcio]

On 4/13/24 19:03, Adam Skladowski wrote:

Add MDSS nodes to support displays on MSM8976 SoC.

Signed-off-by: Adam Skladowski 
---


[...]


+
+   mdp_opp_table: opp-table {
+   compatible = "operating-points-v2";
+
+   opp-17778 {
+   opp-hz = /bits/ 64 <17778>;
+   required-opps = 
<&rpmpd_opp_svs>;
+   };
+
+   opp-27000 {
+   opp-hz = /bits/ 64 <27000>;
+   required-opps = 
<&rpmpd_opp_svs_plus>;
+   };
+
+   opp-32000 {
+   opp-hz = /bits/ 64 <32000>;
+   required-opps = 
<&rpmpd_opp_nom>;
+   };
+   opp-36000 {


Missing a newline above

[...]



+   dsi0_opp_table: opp-table {
+   compatible = "operating-points-v2";
+
+   opp-12500 {
+   opp-hz = /bits/ 64 <12500>;
+   required-opps = 
<&rpmpd_opp_svs>;
+
+   };


You can borrow it from here

Looks reasonable otherwise

Konrad

[PATCH v3 2/4] arm64: dts: qcom: msm8976: Add MDSS nodes

[Adam Skladowski]

Add MDSS nodes to support displays on MSM8976 SoC.

Signed-off-by: Adam Skladowski 
---
 arch/arm64/boot/dts/qcom/msm8976.dtsi | 280 +-
 1 file changed, 276 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi 
b/arch/arm64/boot/dts/qcom/msm8976.dtsi
index 8bdcc1438177..ce15c6ec9f4e 100644
--- a/arch/arm64/boot/dts/qcom/msm8976.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi
@@ -785,10 +785,10 @@ gcc: clock-controller@180 {
 
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
 <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
-<0>,
-<0>,
-<0>,
-<0>;
+<&mdss_dsi0_phy 1>,
+<&mdss_dsi0_phy 0>,
+<&mdss_dsi1_phy 1>,
+<&mdss_dsi1_phy 0>;
clock-names = "xo",
  "xo_a",
  "dsi0pll",
@@ -808,6 +808,278 @@ tcsr: syscon@1937000 {
reg = <0x01937000 0x3>;
};
 
+   mdss: display-subsystem@1a0 {
+   compatible = "qcom,mdss";
+
+   reg = <0x01a0 0x1000>,
+ <0x01ab 0x3000>;
+   reg-names = "mdss_phys", "vbif_phys";
+
+   power-domains = <&gcc MDSS_GDSC>;
+   interrupts = ;
+
+   interrupt-controller;
+   #interrupt-cells = <1>;
+
+   clocks = <&gcc GCC_MDSS_AHB_CLK>,
+<&gcc GCC_MDSS_AXI_CLK>,
+<&gcc GCC_MDSS_VSYNC_CLK>,
+<&gcc GCC_MDSS_MDP_CLK>;
+   clock-names = "iface",
+ "bus",
+ "vsync",
+ "core";
+
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   status = "disabled";
+
+   mdss_mdp: display-controller@1a01000 {
+   compatible = "qcom,msm8976-mdp5", "qcom,mdp5";
+   reg = <0x01a01000 0x89000>;
+   reg-names = "mdp_phys";
+
+   interrupt-parent = <&mdss>;
+   interrupts = <0>;
+
+   clocks = <&gcc GCC_MDSS_AHB_CLK>,
+<&gcc GCC_MDSS_AXI_CLK>,
+<&gcc GCC_MDSS_MDP_CLK>,
+<&gcc GCC_MDSS_VSYNC_CLK>,
+<&gcc GCC_MDP_TBU_CLK>,
+<&gcc GCC_MDP_RT_TBU_CLK>;
+   clock-names = "iface",
+ "bus",
+ "core",
+ "vsync",
+ "tbu",
+ "tbu_rt";
+
+   operating-points-v2 = <&mdp_opp_table>;
+   power-domains = <&gcc MDSS_GDSC>;
+
+   iommus = <&apps_iommu 22>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+
+   mdss_mdp5_intf1_out: endpoint {
+   remote-endpoint = 
<&mdss_dsi0_in>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+
+   mdss_mdp5_intf2_out: endpoint {
+   remote-endpoint = 
<&mdss_dsi1_in>;
+   };
+   };
+   };
+
+   mdp_opp_table: opp-table {
+   compatible = "operating-points-v2";
+
+   opp-17778 {
+   opp-hz = /bits/ 64 <17778>;
+   required-opps = 
<&rpmpd_opp_svs>;
+   };
+
+   opp-27000 {