subject:"\[PATCH v3 20\/25\] ARM\: owl\: Implement CPU enable\-method for S500"

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

2017-03-03 Thread Andreas Färber

Am 01.03.2017 um 11:40 schrieb Andreas Färber:
> Am 01.03.2017 um 08:19 schrieb kbuild test robot:
>> Hi Andreas,
>>
>> [auto build test ERROR on next-20170228]
>> [also build test ERROR on v4.10]
>> [cannot apply to robh/for-next linus/master linux/master v4.9-rc8 v4.9-rc7 
>> v4.9-rc6]
>> [if your patch is applied to the wrong git tree, please drop us a note to 
>> help improve the system]
>>
>> url:
>> https://github.com/0day-ci/linux/commits/Andreas-F-rber/ARM-Initial-Actions-Semi-S500-and-S900-enablement/20170301-110028
>> config: arm-allmodconfig (attached as .config)
>> compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
>> reproduce:
>> wget 
>> https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
>>  -O ~/bin/make.cross
>> chmod +x ~/bin/make.cross
>> # save the attached .config to linux build tree
>> make.cross ARCH=arm 
>>
>> All errors (new ones prefixed by >>):
>>
>>arch/arm/mach-actions/headsmp.S: Assembler messages:
 arch/arm/mach-actions/headsmp.S:43: Error: selected processor does not 
 support `dsb' in ARM mode
 arch/arm/mach-actions/headsmp.S:44: Error: selected processor does not 
 support `isb' in ARM mode
>>
>> vim +43 arch/arm/mach-actions/headsmp.S
>>
>> 37   mov r6, r2, lsl r0
>> 38   orr r5, r5, r6  @ Reg = 
>> (Temp<> 39   mcr p15, 0, r5, c7, c6, 2
>> 40   bgt 2b
>> 41   cmp r2, #0
>> 42   bgt 1b
>>   > 43   dsb
>>   > 44   isb
> 
> Any suggestion what to do about this error? Obviously it built fine for
> me, and the only thing I spotted in the attached config was that it's
> apparently a BE8 build...

And it has V6 enabled. If I set

AFLAGS_headsmp.o := -Wa,-march=armv7-a

then the error seems resolved.

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

2017-03-03 Thread Andreas Färber

Am 01.03.2017 um 11:40 schrieb Andreas Färber:
> Am 01.03.2017 um 08:19 schrieb kbuild test robot:
>> Hi Andreas,
>>
>> [auto build test ERROR on next-20170228]
>> [also build test ERROR on v4.10]
>> [cannot apply to robh/for-next linus/master linux/master v4.9-rc8 v4.9-rc7 
>> v4.9-rc6]
>> [if your patch is applied to the wrong git tree, please drop us a note to 
>> help improve the system]
>>
>> url:
>> https://github.com/0day-ci/linux/commits/Andreas-F-rber/ARM-Initial-Actions-Semi-S500-and-S900-enablement/20170301-110028
>> config: arm-allmodconfig (attached as .config)
>> compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
>> reproduce:
>> wget 
>> https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
>>  -O ~/bin/make.cross
>> chmod +x ~/bin/make.cross
>> # save the attached .config to linux build tree
>> make.cross ARCH=arm 
>>
>> All errors (new ones prefixed by >>):
>>
>>arch/arm/mach-actions/headsmp.S: Assembler messages:
 arch/arm/mach-actions/headsmp.S:43: Error: selected processor does not 
 support `dsb' in ARM mode
 arch/arm/mach-actions/headsmp.S:44: Error: selected processor does not 
 support `isb' in ARM mode
>>
>> vim +43 arch/arm/mach-actions/headsmp.S
>>
>> 37   mov r6, r2, lsl r0
>> 38   orr r5, r5, r6  @ Reg = 
>> (Temp<> 39   mcr p15, 0, r5, c7, c6, 2
>> 40   bgt 2b
>> 41   cmp r2, #0
>> 42   bgt 1b
>>   > 43   dsb
>>   > 44   isb
> 
> Any suggestion what to do about this error? Obviously it built fine for
> me, and the only thing I spotted in the attached config was that it's
> apparently a BE8 build...

And it has V6 enabled. If I set

AFLAGS_headsmp.o := -Wa,-march=armv7-a

then the error seems resolved.

Regards,
Andreas

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

2017-03-01 Thread Andreas Färber

Am 01.03.2017 um 08:19 schrieb kbuild test robot:
> Hi Andreas,
> 
> [auto build test ERROR on next-20170228]
> [also build test ERROR on v4.10]
> [cannot apply to robh/for-next linus/master linux/master v4.9-rc8 v4.9-rc7 
> v4.9-rc6]
> [if your patch is applied to the wrong git tree, please drop us a note to 
> help improve the system]
> 
> url:
> https://github.com/0day-ci/linux/commits/Andreas-F-rber/ARM-Initial-Actions-Semi-S500-and-S900-enablement/20170301-110028
> config: arm-allmodconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
> reproduce:
> wget 
> https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
>  -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm 
> 
> All errors (new ones prefixed by >>):
> 
>arch/arm/mach-actions/headsmp.S: Assembler messages:
>>> arch/arm/mach-actions/headsmp.S:43: Error: selected processor does not 
>>> support `dsb' in ARM mode
>>> arch/arm/mach-actions/headsmp.S:44: Error: selected processor does not 
>>> support `isb' in ARM mode
> 
> vim +43 arch/arm/mach-actions/headsmp.S
> 
> 37mov r6, r2, lsl r0
> 38orr r5, r5, r6  @ Reg = 
> (Temp< 39mcr p15, 0, r5, c7, c6, 2
> 40bgt 2b
> 41cmp r2, #0
> 42bgt 1b
>   > 43dsb
>   > 44isb

Any suggestion what to do about this error? Obviously it built fine for
me, and the only thing I spotted in the attached config was that it's
apparently a BE8 build...

Do we need a Kconfig "depends on" or some #ifdef here? This assembler
part of the code was merely indentation-fixed by me.

Regards,
Andreas

> 45mov pc, lr
> 46ENDPROC(owl_v7_invalidate_l1)
> 47
> 
> ---
> 0-DAY kernel test infrastructureOpen Source Technology Center
> https://lists.01.org/pipermail/kbuild-all   Intel Corporation

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

2017-03-01 Thread Andreas Färber

Am 01.03.2017 um 08:19 schrieb kbuild test robot:
> Hi Andreas,
> 
> [auto build test ERROR on next-20170228]
> [also build test ERROR on v4.10]
> [cannot apply to robh/for-next linus/master linux/master v4.9-rc8 v4.9-rc7 
> v4.9-rc6]
> [if your patch is applied to the wrong git tree, please drop us a note to 
> help improve the system]
> 
> url:
> https://github.com/0day-ci/linux/commits/Andreas-F-rber/ARM-Initial-Actions-Semi-S500-and-S900-enablement/20170301-110028
> config: arm-allmodconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
> reproduce:
> wget 
> https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
>  -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm 
> 
> All errors (new ones prefixed by >>):
> 
>arch/arm/mach-actions/headsmp.S: Assembler messages:
>>> arch/arm/mach-actions/headsmp.S:43: Error: selected processor does not 
>>> support `dsb' in ARM mode
>>> arch/arm/mach-actions/headsmp.S:44: Error: selected processor does not 
>>> support `isb' in ARM mode
> 
> vim +43 arch/arm/mach-actions/headsmp.S
> 
> 37mov r6, r2, lsl r0
> 38orr r5, r5, r6  @ Reg = 
> (Temp< 39mcr p15, 0, r5, c7, c6, 2
> 40bgt 2b
> 41cmp r2, #0
> 42bgt 1b
>   > 43dsb
>   > 44isb

Any suggestion what to do about this error? Obviously it built fine for
me, and the only thing I spotted in the attached config was that it's
apparently a BE8 build...

Do we need a Kconfig "depends on" or some #ifdef here? This assembler
part of the code was merely indentation-fixed by me.

Regards,
Andreas

> 45mov pc, lr
> 46ENDPROC(owl_v7_invalidate_l1)
> 47
> 
> ---
> 0-DAY kernel test infrastructureOpen Source Technology Center
> https://lists.01.org/pipermail/kbuild-all   Intel Corporation

-- 
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

2017-03-01 Thread kbuild test robot

Hi Andreas,

[auto build test ERROR on next-20170228]
[also build test ERROR on v4.10]
[cannot apply to robh/for-next linus/master linux/master v4.9-rc8 v4.9-rc7 
v4.9-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Andreas-F-rber/ARM-Initial-Actions-Semi-S500-and-S900-enablement/20170301-110028
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   arch/arm/mach-actions/headsmp.S: Assembler messages:
>> arch/arm/mach-actions/headsmp.S:43: Error: selected processor does not 
>> support `dsb' in ARM mode
>> arch/arm/mach-actions/headsmp.S:44: Error: selected processor does not 
>> support `isb' in ARM mode

vim +43 arch/arm/mach-actions/headsmp.S

37  mov r6, r2, lsl r0
38  orr r5, r5, r6  @ Reg = 
(Temp< 43  dsb
  > 44  isb
45  mov pc, lr
46  ENDPROC(owl_v7_invalidate_l1)
47  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

2017-03-01 Thread kbuild test robot

Hi Andreas,

[auto build test ERROR on next-20170228]
[also build test ERROR on v4.10]
[cannot apply to robh/for-next linus/master linux/master v4.9-rc8 v4.9-rc7 
v4.9-rc6]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Andreas-F-rber/ARM-Initial-Actions-Semi-S500-and-S900-enablement/20170301-110028
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross
 -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   arch/arm/mach-actions/headsmp.S: Assembler messages:
>> arch/arm/mach-actions/headsmp.S:43: Error: selected processor does not 
>> support `dsb' in ARM mode
>> arch/arm/mach-actions/headsmp.S:44: Error: selected processor does not 
>> support `isb' in ARM mode

vim +43 arch/arm/mach-actions/headsmp.S

37  mov r6, r2, lsl r0
38  orr r5, r5, r6  @ Reg = 
(Temp< 43  dsb
  > 44  isb
45  mov pc, lr
46  ENDPROC(owl_v7_invalidate_l1)
47  

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

[PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

2017-02-27 Thread Andreas Färber

Allow to bring up CPU1.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 arch/arm/mach-actions/Makefile  |   1 +
 arch/arm/mach-actions/headsmp.S |  68 
 arch/arm/mach-actions/platsmp.c | 166 
 3 files changed, 235 insertions(+)
 create mode 100644 arch/arm/mach-actions/headsmp.S
 create mode 100644 arch/arm/mach-actions/platsmp.c

diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile
index 524c381..2fb61f8 100644
--- a/arch/arm/mach-actions/Makefile
+++ b/arch/arm/mach-actions/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_ACTIONS) += owl.o
+obj-${CONFIG_ARCH_ACTIONS} += platsmp.o headsmp.o
diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S
new file mode 100644
index 000..dc4832f
--- /dev/null
+++ b/arch/arm/mach-actions/headsmp.S
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2012 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+
+ENTRY(owl_v7_invalidate_l1)
+   mov r0, #0
+   mcr p15, 0, r0, c7, c5, 0   @ invalidate I cache
+   mcr p15, 2, r0, c0, c0, 0
+   mrc p15, 1, r0, c0, c0, 0
+
+   ldr r1, =0x7fff
+   and r2, r1, r0, lsr #13
+
+   ldr r1, =0x3ff
+
+   and r3, r1, r0, lsr #3  @ NumWays - 1
+   add r2, r2, #1  @ NumSets
+
+   and r0, r0, #0x7
+   add r0, r0, #4  @ SetShift
+
+   clz r1, r3  @ WayShift
+   add r4, r3, #1  @ NumWays
+1: sub r2, r2, #1  @ NumSets--
+   mov r3, r4  @ Temp = NumWays
+2: subsr3, r3, #1  @ Temp--
+   mov r5, r3, lsl r1
+   mov r6, r2, lsl r0
+   orr r5, r5, r6  @ Reg = (Temp< 3)
+   return -EINVAL;
+
+   switch (cpu) {
+   case 2:
+   case 3:
+   /* CPU2/3 are power-gated */
+   return -EINVAL;
+   }
+
+   /* wait for CPUx to run to WFE instruction */
+   udelay(200);
+
+   writel(virt_to_phys(owl_secondary_startup),
+  timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
+   writel(OWL_CPUx_FLAG_BOOT,
+  timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
+
+   dsb_sev();
+   mb();
+
+   return 0;
+}
+
+static int

[PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

2017-02-27 Thread Andreas Färber

Allow to bring up CPU1.

Based on LeMaker linux-actions tree.

Signed-off-by: Andreas Färber 
---
 v3: new
 
 arch/arm/mach-actions/Makefile  |   1 +
 arch/arm/mach-actions/headsmp.S |  68 
 arch/arm/mach-actions/platsmp.c | 166 
 3 files changed, 235 insertions(+)
 create mode 100644 arch/arm/mach-actions/headsmp.S
 create mode 100644 arch/arm/mach-actions/platsmp.c

diff --git a/arch/arm/mach-actions/Makefile b/arch/arm/mach-actions/Makefile
index 524c381..2fb61f8 100644
--- a/arch/arm/mach-actions/Makefile
+++ b/arch/arm/mach-actions/Makefile
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_ACTIONS) += owl.o
+obj-${CONFIG_ARCH_ACTIONS} += platsmp.o headsmp.o
diff --git a/arch/arm/mach-actions/headsmp.S b/arch/arm/mach-actions/headsmp.S
new file mode 100644
index 000..dc4832f
--- /dev/null
+++ b/arch/arm/mach-actions/headsmp.S
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2012 Actions Semi Inc.
+ * Author: Actions Semi, Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include 
+#include 
+
+ENTRY(owl_v7_invalidate_l1)
+   mov r0, #0
+   mcr p15, 0, r0, c7, c5, 0   @ invalidate I cache
+   mcr p15, 2, r0, c0, c0, 0
+   mrc p15, 1, r0, c0, c0, 0
+
+   ldr r1, =0x7fff
+   and r2, r1, r0, lsr #13
+
+   ldr r1, =0x3ff
+
+   and r3, r1, r0, lsr #3  @ NumWays - 1
+   add r2, r2, #1  @ NumSets
+
+   and r0, r0, #0x7
+   add r0, r0, #4  @ SetShift
+
+   clz r1, r3  @ WayShift
+   add r4, r3, #1  @ NumWays
+1: sub r2, r2, #1  @ NumSets--
+   mov r3, r4  @ Temp = NumWays
+2: subsr3, r3, #1  @ Temp--
+   mov r5, r3, lsl r1
+   mov r6, r2, lsl r0
+   orr r5, r5, r6  @ Reg = (Temp<
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define OWL_CPU1_ADDR  0x50
+#define OWL_CPU1_FLAG  0x5c
+
+#define OWL_CPUx_FLAG_BOOT 0x55aa
+
+static void __iomem *scu_base_addr;
+static void __iomem *timer_base_addr;
+static int ncores;
+
+static DEFINE_SPINLOCK(boot_lock);
+
+static void write_pen_release(int val)
+{
+   pen_release = val;
+   smp_wmb();
+   __cpuc_flush_dcache_area((void *)_release, sizeof(pen_release));
+   outer_clean_range(__pa(_release), __pa(_release + 1));
+}
+
+static void s500_smp_secondary_init(unsigned int cpu)
+{
+   /*
+* let the primary processor know we're out of the
+* pen, then head off into the C entry point
+*/
+   write_pen_release(-1);
+
+   spin_lock(_lock);
+   spin_unlock(_lock);
+}
+
+void owl_secondary_startup(void);
+
+static int s500_wakeup_secondary(unsigned int cpu)
+{
+   if (cpu > 3)
+   return -EINVAL;
+
+   switch (cpu) {
+   case 2:
+   case 3:
+   /* CPU2/3 are power-gated */
+   return -EINVAL;
+   }
+
+   /* wait for CPUx to run to WFE instruction */
+   udelay(200);
+
+   writel(virt_to_phys(owl_secondary_startup),
+  timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
+   writel(OWL_CPUx_FLAG_BOOT,
+  timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
+
+   dsb_sev();
+   mb();
+
+   return 0;
+}
+
+static int s500_smp_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+   unsigned long timeout;
+   int ret;
+
+   ret = s500_wakeup_secondary(cpu);
+   if (ret)
+   return ret;
+
+   udelay(10);
+
+   spin_lock(_lock);
+
+   /*
+* The secondary processor is waiting to be released from
+* the holding pen - release it, then wait for it to flag
+* that it has been released by resetting pen_release.
+*/
+   write_pen_release(cpu_logical_map(cpu));
+   smp_send_reschedule(cpu);
+
+   timeout = jiffies + (1 * HZ);
+   while (time_before(jiffies, timeout)) {
+   if (pen_release == -1)
+   break;
+   }
+
+   writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
+   writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
+
+   spin_unlock(_lock);
+
+   return pen_release != -1 ? -ENOSYS : 0;
+}
+
+static void __init s500_smp_prepare_cpus(unsigned int max_cpus)
+{
+   struct device_node *node;
+
+   node = of_find_compatible_node(NULL, NULL, "actions,s500-timer");
+   if (!node) {
+   pr_err("%s: missing timer\n", __func__);
+   return;
+   }
+
+   timer_base_addr = of_iomap(node, 0);
+   if (!timer_base_addr) {
+   pr_err("%s: could not map timer registers\n", __func__);
+   return;
+   }
+
+   if

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

Re: [PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

[PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

[PATCH v3 20/25] ARM: owl: Implement CPU enable-method for S500

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