Re: [PATCH v3 3/3] net/phy: micrel: Center FLP timing at 16ms
On 06/05/2015 05:43 PM, Florian Fainelli wrote: > On 05/06/15 15:40, Jaeden Amero wrote: >> Link failures have been observed when using the KSZ9031 with HP 1810-8G >> and HP 1910-8G network switches. Center the FLP timing at 16ms to help >> avoid intermittent link failures. >> >> From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section >> "Auto-Negotiation Timing": >> The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst >> transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3 >> Standard specifies this timing to be 16ms +/-8ms. Some PHY link >> partners need to receive the FLP with 16ms centered timing; >> otherwise, there can be intermittent link failures and long >> link-up times. >> >> After KSZ9031[RNX or MNX] power-up/reset, program the following >> register sequence to set the FLP timing to 16ms >> >> Write Register Dh = 0x // Set up register address for MMD – Device >> Address 0h >> Write Register Eh = 0x0004 // Select Register 4h of MMD – Device >> Address 0h >> Write Register Dh = 0x4000 // Select register data for MMD – Device >> Address 0h, Register 4h >> Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device >> Address 0h, Register 4h >> Write Register Dh = 0x // Set up register address for MMD – Device >> Address 0h >> Write Register Eh = 0x0003 // Select Register 3h of MMD – Device >> Address 0h >> Write Register Dh = 0x4000 // Select register data for MMD – Device >> Address 0h, Register 3h >> Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device >> Address 0h, Register 3h >> Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation > > Quoting a portion of the data-sheet on how to do this programming is > very strange considering that the code is going to be the reference, not > the commit message. I included it for lack of something better to quote that explained which values to set when. I'd be happy to revise the message as this appears too strange. > Other than that, this looks reasonable. Thanks very much for the review. Cheers, Jaeden -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 3/3] net/phy: micrel: Center FLP timing at 16ms
On 05/06/15 15:40, Jaeden Amero wrote:
> Link failures have been observed when using the KSZ9031 with HP 1810-8G
> and HP 1910-8G network switches. Center the FLP timing at 16ms to help
> avoid intermittent link failures.
>
> From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
> "Auto-Negotiation Timing":
> The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
> transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
> Standard specifies this timing to be 16ms +/-8ms. Some PHY link
> partners need to receive the FLP with 16ms centered timing;
> otherwise, there can be intermittent link failures and long
> link-up times.
>
> After KSZ9031[RNX or MNX] power-up/reset, program the following
> register sequence to set the FLP timing to 16ms
>
> Write Register Dh = 0x // Set up register address for MMD – Device
> Address 0h
> Write Register Eh = 0x0004 // Select Register 4h of MMD – Device
> Address 0h
> Write Register Dh = 0x4000 // Select register data for MMD – Device
> Address 0h, Register 4h
> Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device
> Address 0h, Register 4h
> Write Register Dh = 0x // Set up register address for MMD – Device
> Address 0h
> Write Register Eh = 0x0003 // Select Register 3h of MMD – Device
> Address 0h
> Write Register Dh = 0x4000 // Select register data for MMD – Device
> Address 0h, Register 3h
> Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device
> Address 0h, Register 3h
> Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation
Quoting a portion of the data-sheet on how to do this programming is
very strange considering that the code is going to be the reference, not
the commit message.
Other than that, this looks reasonable.
>
> Signed-off-by: Jaeden Amero
> ---
> drivers/net/phy/micrel.c | 23 ++-
> 1 file changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
> index f23765e..499185e 100644
> --- a/drivers/net/phy/micrel.c
> +++ b/drivers/net/phy/micrel.c
> @@ -366,6 +366,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
> #define KSZ9031_PS_TO_REG60
>
> /* Extended registers */
> +/* MMD Address 0x0 */
> +#define MII_KSZ9031RN_FLP_BURST_TX_LO3
> +#define MII_KSZ9031RN_FLP_BURST_TX_HI4
> +
> /* MMD Address 0x2 */
> #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
> #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
> @@ -427,6 +431,22 @@ static int ksz9031_of_load_skew_values(struct phy_device
> *phydev,
> return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
> }
>
> +static int ksz9031_center_flp_timing(struct phy_device *phydev)
> +{
> + int result;
> +
> + /* Center KSZ9031RNX FLP timing at 16ms. */
> + result = ksz9031_extended_write(phydev, OP_DATA, 0,
> + MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
> + result = ksz9031_extended_write(phydev, OP_DATA, 0,
> + MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
> +
> + if (result)
> + return result;
> +
> + return genphy_restart_aneg(phydev);
> +}
> +
> static int ksz9031_config_init(struct phy_device *phydev)
> {
> const struct device *dev = &phydev->dev;
> @@ -462,7 +482,8 @@ static int ksz9031_config_init(struct phy_device *phydev)
> MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
> tx_data_skews, 4);
> }
> - return 0;
> +
> + return ksz9031_center_flp_timing(phydev);
> }
>
> #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
>
--
Florian
--
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[PATCH v3 3/3] net/phy: micrel: Center FLP timing at 16ms
Link failures have been observed when using the KSZ9031 with HP 1810-8G
and HP 1910-8G network switches. Center the FLP timing at 16ms to help
avoid intermittent link failures.
>From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
"Auto-Negotiation Timing":
The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
Standard specifies this timing to be 16ms +/-8ms. Some PHY link
partners need to receive the FLP with 16ms centered timing;
otherwise, there can be intermittent link failures and long
link-up times.
After KSZ9031[RNX or MNX] power-up/reset, program the following
register sequence to set the FLP timing to 16ms
Write Register Dh = 0x // Set up register address for MMD – Device
Address 0h
Write Register Eh = 0x0004 // Select Register 4h of MMD – Device
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device
Address 0h, Register 4h
Write Register Eh = 0x0006 // Write value 0x0006 to MMD – Device
Address 0h, Register 4h
Write Register Dh = 0x // Set up register address for MMD – Device
Address 0h
Write Register Eh = 0x0003 // Select Register 3h of MMD – Device
Address 0h
Write Register Dh = 0x4000 // Select register data for MMD – Device
Address 0h, Register 3h
Write Register Eh = 0x1A80 // Write value 0x1A80 to MMD – Device
Address 0h, Register 3h
Write Register 0h, Bit [9] = 1 // Restart Auto-Negotiation
Signed-off-by: Jaeden Amero
---
drivers/net/phy/micrel.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index f23765e..499185e 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -366,6 +366,10 @@ static int ksz9021_config_init(struct phy_device *phydev)
#define KSZ9031_PS_TO_REG 60
/* Extended registers */
+/* MMD Address 0x0 */
+#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
+#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
+
/* MMD Address 0x2 */
#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
@@ -427,6 +431,22 @@ static int ksz9031_of_load_skew_values(struct phy_device
*phydev,
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
}
+static int ksz9031_center_flp_timing(struct phy_device *phydev)
+{
+ int result;
+
+ /* Center KSZ9031RNX FLP timing at 16ms. */
+ result = ksz9031_extended_write(phydev, OP_DATA, 0,
+ MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+ result = ksz9031_extended_write(phydev, OP_DATA, 0,
+ MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
+
+ if (result)
+ return result;
+
+ return genphy_restart_aneg(phydev);
+}
+
static int ksz9031_config_init(struct phy_device *phydev)
{
const struct device *dev = &phydev->dev;
@@ -462,7 +482,8 @@ static int ksz9031_config_init(struct phy_device *phydev)
MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
tx_data_skews, 4);
}
- return 0;
+
+ return ksz9031_center_flp_timing(phydev);
}
#define KSZ8873MLL_GLOBAL_CONTROL_40x06
--
2.1.4
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