Re: [PATCH v3 3/4] KVM: SVM: Add support for SVM instruction address check change

2021-01-26 Thread Wei Huang 




On 1/26/21 5:52 AM, Maxim Levitsky wrote:

On Tue, 2021-01-26 at 03:18 -0500, Wei Huang wrote:

New AMD CPUs have a change that checks #VMEXIT intercept on special SVM
instructions before checking their EAX against reserved memory region.
This change is indicated by CPUID_0x800A_EDX[28]. If it is 1, #VMEXIT
is triggered before #GP. KVM doesn't need to intercept and emulate #GP
faults as #GP is supposed to be triggered.

Co-developed-by: Bandan Das 
Signed-off-by: Bandan Das 
Signed-off-by: Wei Huang 
Reviewed-by: Maxim Levitsky 
---
  arch/x86/include/asm/cpufeatures.h | 1 +
  arch/x86/kvm/svm/svm.c | 3 +++
  2 files changed, 4 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h 
b/arch/x86/include/asm/cpufeatures.h
index 84b887825f12..ea89d6fdd79a 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -337,6 +337,7 @@
  #define X86_FEATURE_AVIC  (15*32+13) /* Virtual Interrupt 
Controller */
  #define X86_FEATURE_V_VMSAVE_VMLOAD   (15*32+15) /* Virtual VMSAVE VMLOAD */
  #define X86_FEATURE_VGIF  (15*32+16) /* Virtual GIF */
+#define X86_FEATURE_SVME_ADDR_CHK  (15*32+28) /* "" SVME addr check */
  
  /* Intel-defined CPU features, CPUID level 0x0007:0 (ECX), word 16 */

  #define X86_FEATURE_AVX512VBMI(16*32+ 1) /* AVX512 Vector Bit 
Manipulation instructions*/
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index e5ca01e25e89..f9233c79265b 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -1036,6 +1036,9 @@ static __init int svm_hardware_setup(void)
}
}
  
+	if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))

+   svm_gp_erratum_intercept = false;
+

Again, I would make svm_gp_erratum_intercept a tri-state module param,
and here if it is in 'auto' state do this.



I will try to craft a param patch and see if it flies...

Re: [PATCH v3 3/4] KVM: SVM: Add support for SVM instruction address check change

2021-01-26 Thread Maxim Levitsky 
On Tue, 2021-01-26 at 03:18 -0500, Wei Huang wrote:
> New AMD CPUs have a change that checks #VMEXIT intercept on special SVM
> instructions before checking their EAX against reserved memory region.
> This change is indicated by CPUID_0x800A_EDX[28]. If it is 1, #VMEXIT
> is triggered before #GP. KVM doesn't need to intercept and emulate #GP
> faults as #GP is supposed to be triggered.
> 
> Co-developed-by: Bandan Das 
> Signed-off-by: Bandan Das 
> Signed-off-by: Wei Huang 
> Reviewed-by: Maxim Levitsky 
> ---
>  arch/x86/include/asm/cpufeatures.h | 1 +
>  arch/x86/kvm/svm/svm.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h 
> b/arch/x86/include/asm/cpufeatures.h
> index 84b887825f12..ea89d6fdd79a 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -337,6 +337,7 @@
>  #define X86_FEATURE_AVIC (15*32+13) /* Virtual Interrupt 
> Controller */
>  #define X86_FEATURE_V_VMSAVE_VMLOAD  (15*32+15) /* Virtual VMSAVE VMLOAD */
>  #define X86_FEATURE_VGIF (15*32+16) /* Virtual GIF */
> +#define X86_FEATURE_SVME_ADDR_CHK(15*32+28) /* "" SVME addr check */
>  
>  /* Intel-defined CPU features, CPUID level 0x0007:0 (ECX), word 16 */
>  #define X86_FEATURE_AVX512VBMI   (16*32+ 1) /* AVX512 Vector Bit 
> Manipulation instructions*/
> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> index e5ca01e25e89..f9233c79265b 100644
> --- a/arch/x86/kvm/svm/svm.c
> +++ b/arch/x86/kvm/svm/svm.c
> @@ -1036,6 +1036,9 @@ static __init int svm_hardware_setup(void)
>   }
>   }
>  
> + if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
> + svm_gp_erratum_intercept = false;
> +
Again, I would make svm_gp_erratum_intercept a tri-state module param,
and here if it is in 'auto' state do this.

Also I might as well made this code fail if X86_FEATURE_SVME_ADDR_CHK is set but
user insists on svm_gp_erratum_intercept = true.

>   if (vgif) {
>   if (!boot_cpu_has(X86_FEATURE_VGIF))
>   vgif = false;


Best regards,
Maxim Levitsky

[PATCH v3 3/4] KVM: SVM: Add support for SVM instruction address check change

2021-01-26 Thread Wei Huang 
New AMD CPUs have a change that checks #VMEXIT intercept on special SVM
instructions before checking their EAX against reserved memory region.
This change is indicated by CPUID_0x800A_EDX[28]. If it is 1, #VMEXIT
is triggered before #GP. KVM doesn't need to intercept and emulate #GP
faults as #GP is supposed to be triggered.

Co-developed-by: Bandan Das 
Signed-off-by: Bandan Das 
Signed-off-by: Wei Huang 
Reviewed-by: Maxim Levitsky 
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 arch/x86/kvm/svm/svm.c | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/arch/x86/include/asm/cpufeatures.h 
b/arch/x86/include/asm/cpufeatures.h
index 84b887825f12..ea89d6fdd79a 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -337,6 +337,7 @@
 #define X86_FEATURE_AVIC   (15*32+13) /* Virtual Interrupt 
Controller */
 #define X86_FEATURE_V_VMSAVE_VMLOAD(15*32+15) /* Virtual VMSAVE VMLOAD */
 #define X86_FEATURE_VGIF   (15*32+16) /* Virtual GIF */
+#define X86_FEATURE_SVME_ADDR_CHK  (15*32+28) /* "" SVME addr check */
 
 /* Intel-defined CPU features, CPUID level 0x0007:0 (ECX), word 16 */
 #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit 
Manipulation instructions*/
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index e5ca01e25e89..f9233c79265b 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -1036,6 +1036,9 @@ static __init int svm_hardware_setup(void)
}
}
 
+   if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
+   svm_gp_erratum_intercept = false;
+
if (vgif) {
if (!boot_cpu_has(X86_FEATURE_VGIF))
vgif = false;
-- 
2.27.0