Re: [PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines
On 03/24/2015 03:40 AM, "Stéphane Viau" wrote: Hi Archit, Hi Stephane, On 03/14/2015 01:19 AM, Stephane Viau wrote: Some interfaces (WB, DSI Command Mode) need to be kicked off through a START Signal. This signal needs to be sent at the right time and requests in some cases to keep track of the pipeline status (eg: whether pipeline registers are flushed AND output WB buffers are ready, in case of WB interface). Signed-off-by: Stephane Viau --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 2 + drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 7 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 31 ++-- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 72 +++- drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 13 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 + 7 files changed, 276 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c index c078f30..72c075a 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c @@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = { .ctl = { .count = 5, .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, + .flush_hw_mask = 0x0003, }, .pipe_vig = { .count = 3, @@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = { .ctl = { .count = 5, .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, + .flush_hw_mask = 0x003f, msm8x16 would require a flush_hw_mask too, it should be 0x32a59 if I'm not wrong. Could you please add it for the next revision, or as a part of the 8x16 hw cfg patch? Correct; thanks for pointing this out. IMO, this value should be 0x4003 because the fields are actually present in the register (even though the interfaces/pipes.etc. are not). Anyway, these bits won't be accessed because the driver won't even allow the usage of the corresponding resources. Okay, that makes sense. I will update in the v2 of "drm/msm/mdp5: Add hardware configuration for msm8x16". Thanks, Stephane. Thanks! Archit -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines
Hi Archit, > Hi Stephane, > > On 03/14/2015 01:19 AM, Stephane Viau wrote: >> Some interfaces (WB, DSI Command Mode) need to be kicked off >> through a START Signal. This signal needs to be sent at the right >> time and requests in some cases to keep track of the pipeline >> status (eg: whether pipeline registers are flushed AND output WB >> buffers are ready, in case of WB interface). >> >> Signed-off-by: Stephane Viau >> --- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 2 + >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 7 +- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 31 ++-- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247 >> >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 72 +++- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 13 +- >> drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 + >> 7 files changed, 276 insertions(+), 97 deletions(-) >> >> diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >> b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >> index c078f30..72c075a 100644 >> --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >> +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c >> @@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = { >> .ctl = { >> .count = 5, >> .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, >> +.flush_hw_mask = 0x0003, >> }, >> .pipe_vig = { >> .count = 3, >> @@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = { >> .ctl = { >> .count = 5, >> .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, >> +.flush_hw_mask = 0x003f, > > msm8x16 would require a flush_hw_mask too, it should be 0x32a59 if I'm > not wrong. Could you please add it for the next revision, or as a part > of the 8x16 hw cfg patch? Correct; thanks for pointing this out. IMO, this value should be 0x4003 because the fields are actually present in the register (even though the interfaces/pipes.etc. are not). Anyway, these bits won't be accessed because the driver won't even allow the usage of the corresponding resources. I will update in the v2 of "drm/msm/mdp5: Add hardware configuration for msm8x16". Thanks, Stephane. > > Thanks, > Archit > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > a Linux Foundation Collaborative Project > -- > To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" > in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines
Hi Stephane, On 03/14/2015 01:19 AM, Stephane Viau wrote: Some interfaces (WB, DSI Command Mode) need to be kicked off through a START Signal. This signal needs to be sent at the right time and requests in some cases to keep track of the pipeline status (eg: whether pipeline registers are flushed AND output WB buffers are ready, in case of WB interface). Signed-off-by: Stephane Viau --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 2 + drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 7 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 31 ++-- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 72 +++- drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 13 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 + 7 files changed, 276 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c index c078f30..72c075a 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c @@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = { .ctl = { .count = 5, .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, + .flush_hw_mask = 0x0003, }, .pipe_vig = { .count = 3, @@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = { .ctl = { .count = 5, .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, + .flush_hw_mask = 0x003f, msm8x16 would require a flush_hw_mask too, it should be 0x32a59 if I'm not wrong. Could you please add it for the next revision, or as a part of the 8x16 hw cfg patch? Thanks, Archit -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v3 3/4] drm/msm/mdp5: Add START signal to kick off certain pipelines
Some interfaces (WB, DSI Command Mode) need to be kicked off through a START Signal. This signal needs to be sent at the right time and requests in some cases to keep track of the pipeline status (eg: whether pipeline registers are flushed AND output WB buffers are ready, in case of WB interface). Signed-off-by: Stephane Viau --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c | 2 + drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h | 7 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c| 31 ++-- drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c | 247 drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.h | 72 +++- drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c | 13 +- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 1 + 7 files changed, 276 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c index c078f30..72c075a 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.c @@ -31,6 +31,7 @@ const struct mdp5_cfg_hw msm8x74_config = { .ctl = { .count = 5, .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, + .flush_hw_mask = 0x0003, }, .pipe_vig = { .count = 3, @@ -78,6 +79,7 @@ const struct mdp5_cfg_hw apq8084_config = { .ctl = { .count = 5, .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, + .flush_hw_mask = 0x003f, }, .pipe_vig = { .count = 4, diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h index 4e90740..69e35ac 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_cfg.h @@ -44,6 +44,11 @@ struct mdp5_lm_block { uint32_t nb_stages; /* number of stages per blender */ }; +struct mdp5_ctl_block { + MDP5_SUB_BLOCK_DEFINITION; + uint32_t flush_hw_mask; /* FLUSH register's hardware mask */ +}; + struct mdp5_smp_block { int mmb_count; /* number of SMP MMBs */ int mmb_size; /* MMB: size in bytes */ @@ -55,7 +60,7 @@ struct mdp5_cfg_hw { char *name; struct mdp5_smp_block smp; - struct mdp5_sub_block ctl; + struct mdp5_ctl_block ctl; struct mdp5_sub_block pipe_vig; struct mdp5_sub_block pipe_rgb; struct mdp5_sub_block pipe_dma; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c index 15136f1..9527ad1 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c @@ -82,8 +82,6 @@ static void request_pending(struct drm_crtc *crtc, uint32_t pending) mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank); } -#define mdp5_lm_get_flush(lm) mdp_ctl_flush_mask_lm(lm) - static void crtc_flush(struct drm_crtc *crtc, u32 flush_mask) { struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); @@ -110,8 +108,8 @@ static void crtc_flush_all(struct drm_crtc *crtc) drm_atomic_crtc_for_each_plane(plane, crtc) { flush_mask |= mdp5_plane_get_flush(plane); } - flush_mask |= mdp5_ctl_get_flush(mdp5_crtc->ctl); - flush_mask |= mdp5_lm_get_flush(mdp5_crtc->lm); + + flush_mask |= mdp_ctl_flush_mask_lm(mdp5_crtc->lm); crtc_flush(crtc, flush_mask); } @@ -442,13 +440,14 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); struct drm_device *dev = crtc->dev; struct mdp5_kms *mdp5_kms = get_kms(crtc); - struct drm_gem_object *cursor_bo, *old_bo; + struct drm_gem_object *cursor_bo, *old_bo = NULL; uint32_t blendcfg, cursor_addr, stride; int ret, bpp, lm; unsigned int depth; enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL; uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); uint32_t roi_w, roi_h; + bool cursor_enable = true; unsigned long flags; if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { @@ -461,7 +460,8 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, if (!handle) { DBG("Cursor off"); - return mdp5_ctl_set_cursor(mdp5_crtc->ctl, false); + cursor_enable = false; + goto set_cursor; } cursor_bo = drm_gem_object_lookup(dev, file, handle); @@ -502,11 +502,14 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); - ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, true); - if (ret) +set_cursor: + ret = mdp5_ctl_set_cursor(mdp5_crtc->ctl, 0, cursor_enable); + if (ret) { + dev_err(dev->dev, "failed to %sable cursor: %d\n", + cursor_e