Re: [PATCH v3 4/6] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC

[Stephen Boyd]

On 11/19, Matthew McClintock wrote:
> +
> +/ {
> +
> + clocks {
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + #clock-cells = <0>;
> + };
> + };

The timer should be right here in the SoC file.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 4/6] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC

[Stephen Boyd]

On 11/19, Matthew McClintock wrote:
> +
> +/ {
> +
> + clocks {
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + #clock-cells = <0>;
> + };
> + };

The timer should be right here in the SoC file.

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH v3 4/6] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC

[Matthew McClintock]

From: Matthew McClintock 

Add initial dts files and SoC support for IPQ4019

Signed-off-by: Varadarajan Narayanan 
---

v2
- add sleep_clk

 arch/arm/boot/dts/qcom-ipq4019.dtsi | 115 
 1 file changed, 115 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
new file mode 100644
index 000..fc73822
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019";
+   compatible = "qcom,ipq4019";
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x0>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x1>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x2>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x3>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+   };
+
+   clocks {
+   sleep_clk: sleep_clk {
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   #clock-cells = <0>;
+   };
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   compatible = "simple-bus";
+
+   intc: interrupt-controller@b00 {
+   compatible = "qcom,msm-qgic2";
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   reg = <0x0b00 0x1000>,
+   <0x0b002000 0x1000>;
+   };
+
+   gcc: clock-controller@180 {
+   compatible = "qcom,gcc-ipq4019";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   reg = <0x180 0x6>;
+   };
+
+   tlmm: pinctrl@0x0100 {
+   compatible = "qcom,ipq4019-pinctrl";
+   reg = <0x0100 0x30>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = <0 208 0>;
+   };
+
+   serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = <0 107 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+
+   serial@78b {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78b 0x200>;
+   interrupts = <0 108 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART2_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+   };
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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[PATCH v3 4/6] qcom: ipq4019: Add basic board/dts support for IPQ4019 SoC

[Matthew McClintock]

From: Matthew McClintock 

Add initial dts files and SoC support for IPQ4019

Signed-off-by: Varadarajan Narayanan 
---

v2
- add sleep_clk

 arch/arm/boot/dts/qcom-ipq4019.dtsi | 115 
 1 file changed, 115 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-ipq4019.dtsi

diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi 
b/arch/arm/boot/dts/qcom-ipq4019.dtsi
new file mode 100644
index 000..fc73822
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+
+#include "skeleton.dtsi"
+#include 
+
+/ {
+   model = "Qualcomm Technologies, Inc. IPQ4019";
+   compatible = "qcom,ipq4019";
+   interrupt-parent = <>;
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x0>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@1 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x1>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@2 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x2>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+
+   cpu@3 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a7";
+   reg = <0x3>;
+   clocks = < GCC_APPS_CLK_SRC>;
+   };
+   };
+
+   clocks {
+   sleep_clk: sleep_clk {
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   #clock-cells = <0>;
+   };
+   };
+
+   soc {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   compatible = "simple-bus";
+
+   intc: interrupt-controller@b00 {
+   compatible = "qcom,msm-qgic2";
+   interrupt-controller;
+   #interrupt-cells = <3>;
+   reg = <0x0b00 0x1000>,
+   <0x0b002000 0x1000>;
+   };
+
+   gcc: clock-controller@180 {
+   compatible = "qcom,gcc-ipq4019";
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   reg = <0x180 0x6>;
+   };
+
+   tlmm: pinctrl@0x0100 {
+   compatible = "qcom,ipq4019-pinctrl";
+   reg = <0x0100 0x30>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   interrupts = <0 208 0>;
+   };
+
+   serial@78af000 {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78af000 0x200>;
+   interrupts = <0 107 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART1_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+
+   serial@78b {
+   compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+   reg = <0x78b 0x200>;
+   interrupts = <0 108 0>;
+   status = "disabled";
+   clocks = < GCC_BLSP1_UART2_APPS_CLK>,
+   < GCC_BLSP1_AHB_CLK>;
+   clock-names = "core", "iface";
+   };
+   };
+};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

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