Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
On 09/02/2021 16:38, Enric Balletbo Serra wrote: > Hi Yongqiang Niu, > > Thank you for your patch. > > Missatge de Yongqiang Niu del dia dt., 5 > de gen. 2021 a les 4:07: >> >> the mmsys will more and more complicated after support >> more and more SoCs, add an independent folder will be >> more clear >> >> Signed-off-by: Yongqiang Niu >> --- >> drivers/soc/mediatek/Makefile | 2 +- > > It will not apply cleanly anymore after the below commit that is > already queued. Maybe you could rebase the patches and resend them > again? > Please don't do that, as I pointed out in [1] I don't like the approach of a new folder. If you disagree please let me know why. Otherwise please send a new version with the changes suggested by me :) Regards, Matthias [1] https://lore.kernel.org/linux-mediatek/4cadc9f0-0761-7609-abac-d2211b097...@gmail.com/ > commit e1e4f7fea37572f0ccf3887430e52c491e9accb6 > Author: CK Hu > Date: Tue Jul 21 15:46:06 2020 +0800 > > soc / drm: mediatek: Move mtk mutex driver to soc folder > > mtk mutex is used by DRM and MDP driver, and its function is SoC-specific, > so move it to soc folder. > > With that fixed, > > Reviewed-by: Enric Balletbo i Serra > > Thanks, > Enric > >> drivers/soc/mediatek/mmsys/Makefile| 2 + >> drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 >> + >> drivers/soc/mediatek/mtk-mmsys.c | 373 >> - >> 4 files changed, 376 insertions(+), 374 deletions(-) >> create mode 100644 drivers/soc/mediatek/mmsys/Makefile >> create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c >> delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c >> >> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile >> index b6908db..eca9774 100644 >> --- a/drivers/soc/mediatek/Makefile >> +++ b/drivers/soc/mediatek/Makefile >> @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o >> obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o >> obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o >> obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o >> -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o >> +obj-$(CONFIG_MTK_MMSYS) += mmsys/ >> diff --git a/drivers/soc/mediatek/mmsys/Makefile >> b/drivers/soc/mediatek/mmsys/Makefile >> new file mode 100644 >> index 000..f44eadc >> --- /dev/null >> +++ b/drivers/soc/mediatek/mmsys/Makefile >> @@ -0,0 +1,2 @@ >> +# SPDX-License-Identifier: GPL-2.0-only >> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o >> diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c >> b/drivers/soc/mediatek/mmsys/mtk-mmsys.c >> new file mode 100644 >> index 000..18f9397 >> --- /dev/null >> +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c >> @@ -0,0 +1,373 @@ >> +// SPDX-License-Identifier: GPL-2.0-only >> +/* >> + * Copyright (c) 2014 MediaTek Inc. >> + * Author: James Liao >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 >> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 >> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048 >> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c >> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 >> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 >> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 >> +#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4 >> +#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8 >> +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac >> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8 >> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 >> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 >> +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 >> + >> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 >> +#define DISP_REG_CONFIG_OUT_SEL0x04c >> +#define DISP_REG_CONFIG_DSI_SEL0x050 >> +#define DISP_REG_CONFIG_DPI_SEL0x064 >> + >> +#define OVL0_MOUT_EN_COLOR00x1 >> +#define OD_MOUT_EN_RDMA0 0x1 >> +#define OD1_MOUT_EN_RDMA1 BIT(16) >> +#define UFOE_MOUT_EN_DSI0 0x1 >> +#define COLOR0_SEL_IN_OVL0 0x1 >> +#define OVL1_MOUT_EN_COLOR10x1 >> +#define GAMMA_MOUT_EN_RDMA10x1 >> +#define RDMA0_SOUT_DPI00x2 >> +#define RDMA0_SOUT_DPI10x3 >> +#define RDMA0_SOUT_DSI10x1 >> +#define RDMA0_SOUT_DSI20x4 >> +#define RDMA0_SOUT_DSI30x5 >> +#define RDMA1_SOUT_DPI00x2 >> +#define RDMA1_SOUT_DPI10x3 >> +#define RDMA1_SOUT_DSI10x1 >> +#define RDMA1_SOUT_DSI20x4 >>
Re: [PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
Hi Yongqiang Niu, Thank you for your patch. Missatge de Yongqiang Niu del dia dt., 5 de gen. 2021 a les 4:07: > > the mmsys will more and more complicated after support > more and more SoCs, add an independent folder will be > more clear > > Signed-off-by: Yongqiang Niu > --- > drivers/soc/mediatek/Makefile | 2 +- It will not apply cleanly anymore after the below commit that is already queued. Maybe you could rebase the patches and resend them again? commit e1e4f7fea37572f0ccf3887430e52c491e9accb6 Author: CK Hu Date: Tue Jul 21 15:46:06 2020 +0800 soc / drm: mediatek: Move mtk mutex driver to soc folder mtk mutex is used by DRM and MDP driver, and its function is SoC-specific, so move it to soc folder. With that fixed, Reviewed-by: Enric Balletbo i Serra Thanks, Enric > drivers/soc/mediatek/mmsys/Makefile| 2 + > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 > + > drivers/soc/mediatek/mtk-mmsys.c | 373 > - > 4 files changed, 376 insertions(+), 374 deletions(-) > create mode 100644 drivers/soc/mediatek/mmsys/Makefile > create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c > delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c > > diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile > index b6908db..eca9774 100644 > --- a/drivers/soc/mediatek/Makefile > +++ b/drivers/soc/mediatek/Makefile > @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o > obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o > obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o > obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o > -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > +obj-$(CONFIG_MTK_MMSYS) += mmsys/ > diff --git a/drivers/soc/mediatek/mmsys/Makefile > b/drivers/soc/mediatek/mmsys/Makefile > new file mode 100644 > index 000..f44eadc > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o > diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c > b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > new file mode 100644 > index 000..18f9397 > --- /dev/null > +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c > @@ -0,0 +1,373 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) 2014 MediaTek Inc. > + * Author: James Liao > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048 > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 > +#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4 > +#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8 > +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8 > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 > +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 > + > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 > +#define DISP_REG_CONFIG_OUT_SEL0x04c > +#define DISP_REG_CONFIG_DSI_SEL0x050 > +#define DISP_REG_CONFIG_DPI_SEL0x064 > + > +#define OVL0_MOUT_EN_COLOR00x1 > +#define OD_MOUT_EN_RDMA0 0x1 > +#define OD1_MOUT_EN_RDMA1 BIT(16) > +#define UFOE_MOUT_EN_DSI0 0x1 > +#define COLOR0_SEL_IN_OVL0 0x1 > +#define OVL1_MOUT_EN_COLOR10x1 > +#define GAMMA_MOUT_EN_RDMA10x1 > +#define RDMA0_SOUT_DPI00x2 > +#define RDMA0_SOUT_DPI10x3 > +#define RDMA0_SOUT_DSI10x1 > +#define RDMA0_SOUT_DSI20x4 > +#define RDMA0_SOUT_DSI30x5 > +#define RDMA1_SOUT_DPI00x2 > +#define RDMA1_SOUT_DPI10x3 > +#define RDMA1_SOUT_DSI10x1 > +#define RDMA1_SOUT_DSI20x4 > +#define RDMA1_SOUT_DSI30x5 > +#define RDMA2_SOUT_DPI00x2 > +#define RDMA2_SOUT_DPI10x3 > +#define RDMA2_SOUT_DSI10x1 > +#define RDMA2_SOUT_DSI20x4 > +#define RDMA2_SOUT_DSI30x5 > +#define DPI0_SEL_IN_RDMA1 0x1 > +#define DPI0_SEL_IN_RDMA2 0x3 > +#define DPI1_SEL_IN_RDMA1
[PATCH v4, 01/10] soc: mediatek: mmsys: create mmsys folder
the mmsys will more and more complicated after support more and more SoCs, add an independent folder will be more clear Signed-off-by: Yongqiang Niu --- drivers/soc/mediatek/Makefile | 2 +- drivers/soc/mediatek/mmsys/Makefile| 2 + drivers/soc/mediatek/mmsys/mtk-mmsys.c | 373 + drivers/soc/mediatek/mtk-mmsys.c | 373 - 4 files changed, 376 insertions(+), 374 deletions(-) create mode 100644 drivers/soc/mediatek/mmsys/Makefile create mode 100644 drivers/soc/mediatek/mmsys/mtk-mmsys.c delete mode 100644 drivers/soc/mediatek/mtk-mmsys.c diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile index b6908db..eca9774 100644 --- a/drivers/soc/mediatek/Makefile +++ b/drivers/soc/mediatek/Makefile @@ -5,4 +5,4 @@ obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o obj-$(CONFIG_MTK_SCPSYS_PM_DOMAINS) += mtk-pm-domains.o -obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o +obj-$(CONFIG_MTK_MMSYS) += mmsys/ diff --git a/drivers/soc/mediatek/mmsys/Makefile b/drivers/soc/mediatek/mmsys/Makefile new file mode 100644 index 000..f44eadc --- /dev/null +++ b/drivers/soc/mediatek/mmsys/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o diff --git a/drivers/soc/mediatek/mmsys/mtk-mmsys.c b/drivers/soc/mediatek/mmsys/mtk-mmsys.c new file mode 100644 index 000..18f9397 --- /dev/null +++ b/drivers/soc/mediatek/mmsys/mtk-mmsys.c @@ -0,0 +1,373 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: James Liao + */ + +#include +#include +#include +#include +#include + +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040 +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN0x048 +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 +#define DISP_REG_CONFIG_DSIE_SEL_IN0x0a4 +#define DISP_REG_CONFIG_DSIO_SEL_IN0x0a8 +#define DISP_REG_CONFIG_DPI_SEL_IN 0x0ac +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT0x0b8 +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN 0x0c4 +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8 +#define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 + +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN 0x030 +#define DISP_REG_CONFIG_OUT_SEL0x04c +#define DISP_REG_CONFIG_DSI_SEL0x050 +#define DISP_REG_CONFIG_DPI_SEL0x064 + +#define OVL0_MOUT_EN_COLOR00x1 +#define OD_MOUT_EN_RDMA0 0x1 +#define OD1_MOUT_EN_RDMA1 BIT(16) +#define UFOE_MOUT_EN_DSI0 0x1 +#define COLOR0_SEL_IN_OVL0 0x1 +#define OVL1_MOUT_EN_COLOR10x1 +#define GAMMA_MOUT_EN_RDMA10x1 +#define RDMA0_SOUT_DPI00x2 +#define RDMA0_SOUT_DPI10x3 +#define RDMA0_SOUT_DSI10x1 +#define RDMA0_SOUT_DSI20x4 +#define RDMA0_SOUT_DSI30x5 +#define RDMA1_SOUT_DPI00x2 +#define RDMA1_SOUT_DPI10x3 +#define RDMA1_SOUT_DSI10x1 +#define RDMA1_SOUT_DSI20x4 +#define RDMA1_SOUT_DSI30x5 +#define RDMA2_SOUT_DPI00x2 +#define RDMA2_SOUT_DPI10x3 +#define RDMA2_SOUT_DSI10x1 +#define RDMA2_SOUT_DSI20x4 +#define RDMA2_SOUT_DSI30x5 +#define DPI0_SEL_IN_RDMA1 0x1 +#define DPI0_SEL_IN_RDMA2 0x3 +#define DPI1_SEL_IN_RDMA1 (0x1 << 8) +#define DPI1_SEL_IN_RDMA2 (0x3 << 8) +#define DSI0_SEL_IN_RDMA1 0x1 +#define DSI0_SEL_IN_RDMA2 0x4 +#define DSI1_SEL_IN_RDMA1 0x1 +#define DSI1_SEL_IN_RDMA2 0x4 +#define DSI2_SEL_IN_RDMA1 (0x1 << 16) +#define DSI2_SEL_IN_RDMA2 (0x4 << 16) +#define DSI3_SEL_IN_RDMA1 (0x1 << 16) +#define DSI3_SEL_IN_RDMA2 (0x4 << 16) +#define COLOR1_SEL_IN_OVL1 0x1 + +#define OVL_MOUT_EN_RDMA 0x1 +#define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 +#define BLS_TO_DPI_RDMA1_TO_DSI0x2 +#define DSI_SEL_IN_BLS 0x0 +#define
