Re: [PATCH v4] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

[Jacek Tomaka]

> On 2 Aug 2018, at 6:07 pm, Thomas Gleixner  wrote:
> 
> The actiual purpose of sending V4 which is identical to V3 is?
> 
>> 
>> Signed-off-by: Jacek Tomaka 
>> ---

Yes, thanks. I missed it initially, sorry.

> It's good practice to add a
> 
> V3 -> V4: changed foo
> V2 -> V3: fixed bla
> ...
> 
> section to patches which have more than one version.

Sure. Would you like me to send it for this patch as well? 

Regards.
Jacek Tomaka

Re: [PATCH v4] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

[Thomas Gleixner]

On Thu, 2 Aug 2018, Jacek Tomaka wrote:

The actiual purpose of sending V4 which is identical to V3 is?

> 
> Signed-off-by: Jacek Tomaka 
> ---

It's good practice to add a

V3 -> V4: changed foo
V2 -> V3: fixed bla
...

section to patches which have more than one version.

Thanks,

tglx

[PATCH v4] perf/x86/intel: Add support for MISPREDICT bit on Knights Landing cpus

[Jacek Tomaka]

From: Jacek Tomaka 

Problem: perf did not show branch predicted/mispredicted bit in brstack.

Output of perf -F brstack for profile collected

Before:
0x4fdbcd/0x4fdc03/-/-/-/0
0x45f4c1/0x4fdba0/-/-/-/0
0x45f544/0x45f4bb/-/-/-/0
0x45f555/0x45f53c/-/-/-/0
0x7f66901cc24b/0x45f555/-/-/-/0
0x7f66901cc22e/0x7f66901cc23d/-/-/-/0
0x7f66901cc1ff/0x7f66901cc20f/-/-/-/0
0x7f66901cc1e8/0x7f66901cc1fc/-/-/-/0

After:
0x4fdbcd/0x4fdc03/P/-/-/0
0x45f4c1/0x4fdba0/P/-/-/0
0x45f544/0x45f4bb/P/-/-/0
0x45f555/0x45f53c/P/-/-/0
0x7f66901cc24b/0x45f555/P/-/-/0
0x7f66901cc22e/0x7f66901cc23d/P/-/-/0
0x7f66901cc1ff/0x7f66901cc20f/P/-/-/0
0x7f66901cc1e8/0x7f66901cc1fc/P/-/-/0

Cause:
As mentioned in Software Development Manual vol 3, 17.4.8.1,
IA32_PERF_CAPABILITIES[5:0] indicates the format of the address that is
stored in the LBR stack. Knights Landing reports 1 (LBR_FORMAT_LIP) as
its format. Despite that, registers containing FROM address of the branch,
do have MISPREDICT bit but because of the format indicated in
IA32_PERF_CAPABILITIES[5:0], LBR did not read MISPREDICT bit.

Solution:
Teach LBR about above Knights Landing quirk and make it read MISPREDICT bit.

Signed-off-by: Jacek Tomaka 
---
 arch/x86/events/intel/lbr.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index cf372b9055..81fe5047c6 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -1230,4 +1230,8 @@ void intel_pmu_lbr_init_knl(void)
 
x86_pmu.lbr_sel_mask = LBR_SEL_MASK;
x86_pmu.lbr_sel_map  = snb_lbr_sel_map;
+
+   /* Knights Landing does have MISPREDICT bit */
+   if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_LIP)
+   x86_pmu.intel_cap.lbr_format = LBR_FORMAT_EIP_FLAGS;
 }
-- 
2.17.0