Re: [PATCH v4] remoteproc/mediatek: Add support for mt8192 SCP
Hi Shih,
On Wed, 14 Oct 2020 at 23:35, Pi-Hsun Shih wrote:
>
> Add support for mt8192 SCP.
>
This is a very thin changelog. I wouldn't be surprised if you get asked to beef
it up.
> Signed-off-by: Pi-Hsun Shih
> Reviewed-by: Tzung-Bi Shih
>
> ---
>
> Change since v3:
> * Remove unnecessary barrier and readl in mt8192_scp_before_load, which
> also fixes build failure on linux-next because of COMPILE_TEST trying
> to compile this on other platforms.
>
> Change since v2:
> * Inline scp_reset_assert / scp_reset_deassert.
>
> Change since v1:
> * Remove unused register definitions.
>
> ---
> drivers/remoteproc/mtk_common.h | 32 +
> drivers/remoteproc/mtk_scp.c | 200 +--
> drivers/remoteproc/mtk_scp_ipi.c | 6 +-
> 3 files changed, 200 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
> index 0066c83636d0..47b4561443a9 100644
> --- a/drivers/remoteproc/mtk_common.h
> +++ b/drivers/remoteproc/mtk_common.h
> @@ -32,6 +32,23 @@
> #define MT8183_SCP_CACHESIZE_8KB BIT(8)
> #define MT8183_SCP_CACHE_CON_WAYEN BIT(10)
>
> +#define MT8192_L2TCM_SRAM_PD_0 0x210C0
> +#define MT8192_L2TCM_SRAM_PD_1 0x210C4
> +#define MT8192_L2TCM_SRAM_PD_2 0x210C8
> +#define MT8192_L1TCM_SRAM_PDN 0x2102C
> +#define MT8192_CPU0_SRAM_PD0x21080
> +
> +#define MT8192_SCP2APMCU_IPC_SET 0x24080
> +#define MT8192_SCP2APMCU_IPC_CLR 0x24084
> +#define MT8192_SCP_IPC_INT_BIT BIT(0)
> +#define MT8192_SCP2SPM_IPC_CLR 0x24094
> +#define MT8192_GIPC_IN_SET 0x24098
> +#define MT8192_HOST_IPC_INT_BITBIT(0)
> +
> +#define MT8192_CORE0_SW_RSTN_CLR 0x3
> +#define MT8192_CORE0_SW_RSTN_SET 0x30004
> +#define MT8192_CORE0_WDT_CFG 0x30034
> +
> #define SCP_FW_VER_LEN 32
> #define SCP_SHARE_BUFFER_SIZE 288
>
> @@ -50,6 +67,19 @@ struct scp_ipi_desc {
> void *priv;
> };
>
> +struct mtk_scp;
> +
> +struct mtk_scp_of_data {
> + int (*scp_before_load)(struct mtk_scp *scp);
> + void (*scp_irq_handler)(struct mtk_scp *scp);
> + void (*scp_reset_assert)(struct mtk_scp *scp);
> + void (*scp_reset_deassert)(struct mtk_scp *scp);
> + void (*scp_stop)(struct mtk_scp *scp);
> +
> + u32 host_to_scp_reg;
> + u32 host_to_scp_int_bit;
> +};
> +
> struct mtk_scp {
> struct device *dev;
> struct rproc *rproc;
> @@ -58,6 +88,8 @@ struct mtk_scp {
> void __iomem *sram_base;
> size_t sram_size;
>
> + const struct mtk_scp_of_data *data;
> +
> struct mtk_share_obj __iomem *recv_buf;
> struct mtk_share_obj __iomem *send_buf;
> struct scp_run run;
> diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
> index ac13e7b046a6..f8c54a0b33fc 100644
> --- a/drivers/remoteproc/mtk_scp.c
> +++ b/drivers/remoteproc/mtk_scp.c
> @@ -2,7 +2,6 @@
> //
> // Copyright (c) 2019 MediaTek Inc.
>
> -#include
> #include
> #include
> #include
> @@ -124,9 +123,6 @@ static int scp_ipi_init(struct mtk_scp *scp)
> size_t send_offset = SCP_FW_END - sizeof(struct mtk_share_obj);
> size_t recv_offset = send_offset - sizeof(struct mtk_share_obj);
>
> - /* Disable SCP to host interrupt */
> - writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);
> -
This needs to be in a patch on its own.
> /* shared buffer initialization */
> scp->recv_buf =
> (struct mtk_share_obj __iomem *)(scp->sram_base +
> recv_offset);
> @@ -138,7 +134,7 @@ static int scp_ipi_init(struct mtk_scp *scp)
> return 0;
> }
>
> -static void scp_reset_assert(const struct mtk_scp *scp)
> +static void mt8183_scp_reset_assert(struct mtk_scp *scp)
Rebranding of functions in preparation for mt8192 needs to be in a separate
patch (in the same patchset). When that is done you can add support for mt8192.
> {
> u32 val;
>
> @@ -147,7 +143,7 @@ static void scp_reset_assert(const struct mtk_scp *scp)
> writel(val, scp->reg_base + MT8183_SW_RSTN);
> }
>
> -static void scp_reset_deassert(const struct mtk_scp *scp)
> +static void mt8183_scp_reset_deassert(struct mtk_scp *scp)
> {
> u32 val;
>
> @@ -156,17 +152,19 @@ static void scp_reset_deassert(const struct mtk_scp
> *scp)
> writel(val, scp->reg_base + MT8183_SW_RSTN);
> }
>
> -static irqreturn_t scp_irq_handler(int irq, void *priv)
> +static void mt8192_scp_reset_assert(struct mtk_scp *scp)
> {
> - struct mtk_scp *scp = priv;
> - u32 scp_to_host;
> - int ret;
> + writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
> +}
>
> - ret = clk_prepare_enable(scp->clk);
> - if (ret) {
> - dev_err(scp->dev, "failed to enable clocks\n");
> - return IRQ_NONE;
> - }
> +static void mt8192_scp_reset_deassert(struct
[PATCH v4] remoteproc/mediatek: Add support for mt8192 SCP
Add support for mt8192 SCP.
Signed-off-by: Pi-Hsun Shih
Reviewed-by: Tzung-Bi Shih
---
Change since v3:
* Remove unnecessary barrier and readl in mt8192_scp_before_load, which
also fixes build failure on linux-next because of COMPILE_TEST trying
to compile this on other platforms.
Change since v2:
* Inline scp_reset_assert / scp_reset_deassert.
Change since v1:
* Remove unused register definitions.
---
drivers/remoteproc/mtk_common.h | 32 +
drivers/remoteproc/mtk_scp.c | 200 +--
drivers/remoteproc/mtk_scp_ipi.c | 6 +-
3 files changed, 200 insertions(+), 38 deletions(-)
diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h
index 0066c83636d0..47b4561443a9 100644
--- a/drivers/remoteproc/mtk_common.h
+++ b/drivers/remoteproc/mtk_common.h
@@ -32,6 +32,23 @@
#define MT8183_SCP_CACHESIZE_8KB BIT(8)
#define MT8183_SCP_CACHE_CON_WAYEN BIT(10)
+#define MT8192_L2TCM_SRAM_PD_0 0x210C0
+#define MT8192_L2TCM_SRAM_PD_1 0x210C4
+#define MT8192_L2TCM_SRAM_PD_2 0x210C8
+#define MT8192_L1TCM_SRAM_PDN 0x2102C
+#define MT8192_CPU0_SRAM_PD0x21080
+
+#define MT8192_SCP2APMCU_IPC_SET 0x24080
+#define MT8192_SCP2APMCU_IPC_CLR 0x24084
+#define MT8192_SCP_IPC_INT_BIT BIT(0)
+#define MT8192_SCP2SPM_IPC_CLR 0x24094
+#define MT8192_GIPC_IN_SET 0x24098
+#define MT8192_HOST_IPC_INT_BITBIT(0)
+
+#define MT8192_CORE0_SW_RSTN_CLR 0x3
+#define MT8192_CORE0_SW_RSTN_SET 0x30004
+#define MT8192_CORE0_WDT_CFG 0x30034
+
#define SCP_FW_VER_LEN 32
#define SCP_SHARE_BUFFER_SIZE 288
@@ -50,6 +67,19 @@ struct scp_ipi_desc {
void *priv;
};
+struct mtk_scp;
+
+struct mtk_scp_of_data {
+ int (*scp_before_load)(struct mtk_scp *scp);
+ void (*scp_irq_handler)(struct mtk_scp *scp);
+ void (*scp_reset_assert)(struct mtk_scp *scp);
+ void (*scp_reset_deassert)(struct mtk_scp *scp);
+ void (*scp_stop)(struct mtk_scp *scp);
+
+ u32 host_to_scp_reg;
+ u32 host_to_scp_int_bit;
+};
+
struct mtk_scp {
struct device *dev;
struct rproc *rproc;
@@ -58,6 +88,8 @@ struct mtk_scp {
void __iomem *sram_base;
size_t sram_size;
+ const struct mtk_scp_of_data *data;
+
struct mtk_share_obj __iomem *recv_buf;
struct mtk_share_obj __iomem *send_buf;
struct scp_run run;
diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c
index ac13e7b046a6..f8c54a0b33fc 100644
--- a/drivers/remoteproc/mtk_scp.c
+++ b/drivers/remoteproc/mtk_scp.c
@@ -2,7 +2,6 @@
//
// Copyright (c) 2019 MediaTek Inc.
-#include
#include
#include
#include
@@ -124,9 +123,6 @@ static int scp_ipi_init(struct mtk_scp *scp)
size_t send_offset = SCP_FW_END - sizeof(struct mtk_share_obj);
size_t recv_offset = send_offset - sizeof(struct mtk_share_obj);
- /* Disable SCP to host interrupt */
- writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);
-
/* shared buffer initialization */
scp->recv_buf =
(struct mtk_share_obj __iomem *)(scp->sram_base + recv_offset);
@@ -138,7 +134,7 @@ static int scp_ipi_init(struct mtk_scp *scp)
return 0;
}
-static void scp_reset_assert(const struct mtk_scp *scp)
+static void mt8183_scp_reset_assert(struct mtk_scp *scp)
{
u32 val;
@@ -147,7 +143,7 @@ static void scp_reset_assert(const struct mtk_scp *scp)
writel(val, scp->reg_base + MT8183_SW_RSTN);
}
-static void scp_reset_deassert(const struct mtk_scp *scp)
+static void mt8183_scp_reset_deassert(struct mtk_scp *scp)
{
u32 val;
@@ -156,17 +152,19 @@ static void scp_reset_deassert(const struct mtk_scp *scp)
writel(val, scp->reg_base + MT8183_SW_RSTN);
}
-static irqreturn_t scp_irq_handler(int irq, void *priv)
+static void mt8192_scp_reset_assert(struct mtk_scp *scp)
{
- struct mtk_scp *scp = priv;
- u32 scp_to_host;
- int ret;
+ writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_SET);
+}
- ret = clk_prepare_enable(scp->clk);
- if (ret) {
- dev_err(scp->dev, "failed to enable clocks\n");
- return IRQ_NONE;
- }
+static void mt8192_scp_reset_deassert(struct mtk_scp *scp)
+{
+ writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR);
+}
+
+static void mt8183_scp_irq_handler(struct mtk_scp *scp)
+{
+ u32 scp_to_host;
scp_to_host = readl(scp->reg_base + MT8183_SCP_TO_HOST);
if (scp_to_host & MT8183_SCP_IPC_INT_BIT)
@@ -177,6 +175,40 @@ static irqreturn_t scp_irq_handler(int irq, void *priv)
/* SCP won't send another interrupt until we set SCP_TO_HOST to 0. */
writel(MT8183_SCP_IPC_INT_BIT | MT8183_SCP_WDT_INT_BIT,
scp->reg_base + MT8183_SCP_TO_HOST);
+}
+
+static void mt8192_scp_irq_handler(struct
