Re: [PATCH v4 0/2] FPGA: TS-7300 FPGA manager
On Mon, 19 Dec 2016, Florian Fainelli wrote: > On 12/18/2016 12:21 PM, Florian Fainelli wrote: > > Hi all, > > > > This patch series adds support for loading bitstreams into the Altera > > Cyclone II > > connected to an EP9302 on a TS-7300 board. > > > > Changes in v4: > > > > - fixed ops->write not to do the final configuration release > > - reordered patches > > > > Changes in v3: > > > > - fix write_init and write_complete signatures > > > > Changes in v2: > > > > - rebased against fpga/for-next > > - added defines for configuration bits and delays > > - added error mesage if ioremap() fails > > - detailed how the configuration through CPLD is done > > Alan, Moritz, thanks for providing Acked-by, I was under the impression > these patches would be taken by you through the FPGA tree, Hi Florain, That's right, I'll handle it. The FPGA tree goes in through Greg. We're in the merge window where stuff Greg already has is going to Linus so it's too late to get this into 4.10. I'll be doing a pull after that. Alan > since Hartley > acked the EP93xx part and since that was the tree used as a baseline. > > Let me know how you want to proceed, since EP93xx is not as active as > other ARM SoCs, there may not be a specific tree where to stage these > patches (unless you take them). > > Thanks! > -- > Florian > -- > To unsubscribe from this list: send the line "unsubscribe linux-fpga" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >
Re: [PATCH v4 0/2] FPGA: TS-7300 FPGA manager
On Mon, 19 Dec 2016, Florian Fainelli wrote: > On 12/18/2016 12:21 PM, Florian Fainelli wrote: > > Hi all, > > > > This patch series adds support for loading bitstreams into the Altera > > Cyclone II > > connected to an EP9302 on a TS-7300 board. > > > > Changes in v4: > > > > - fixed ops->write not to do the final configuration release > > - reordered patches > > > > Changes in v3: > > > > - fix write_init and write_complete signatures > > > > Changes in v2: > > > > - rebased against fpga/for-next > > - added defines for configuration bits and delays > > - added error mesage if ioremap() fails > > - detailed how the configuration through CPLD is done > > Alan, Moritz, thanks for providing Acked-by, I was under the impression > these patches would be taken by you through the FPGA tree, Hi Florain, That's right, I'll handle it. The FPGA tree goes in through Greg. We're in the merge window where stuff Greg already has is going to Linus so it's too late to get this into 4.10. I'll be doing a pull after that. Alan > since Hartley > acked the EP93xx part and since that was the tree used as a baseline. > > Let me know how you want to proceed, since EP93xx is not as active as > other ARM SoCs, there may not be a specific tree where to stage these > patches (unless you take them). > > Thanks! > -- > Florian > -- > To unsubscribe from this list: send the line "unsubscribe linux-fpga" in > the body of a message to majord...@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html >
Re: [PATCH v4 0/2] FPGA: TS-7300 FPGA manager
On 12/18/2016 12:21 PM, Florian Fainelli wrote: > Hi all, > > This patch series adds support for loading bitstreams into the Altera Cyclone > II > connected to an EP9302 on a TS-7300 board. > > Changes in v4: > > - fixed ops->write not to do the final configuration release > - reordered patches > > Changes in v3: > > - fix write_init and write_complete signatures > > Changes in v2: > > - rebased against fpga/for-next > - added defines for configuration bits and delays > - added error mesage if ioremap() fails > - detailed how the configuration through CPLD is done Alan, Moritz, thanks for providing Acked-by, I was under the impression these patches would be taken by you through the FPGA tree, since Hartley acked the EP93xx part and since that was the tree used as a baseline. Let me know how you want to proceed, since EP93xx is not as active as other ARM SoCs, there may not be a specific tree where to stage these patches (unless you take them). Thanks! -- Florian
Re: [PATCH v4 0/2] FPGA: TS-7300 FPGA manager
On 12/18/2016 12:21 PM, Florian Fainelli wrote: > Hi all, > > This patch series adds support for loading bitstreams into the Altera Cyclone > II > connected to an EP9302 on a TS-7300 board. > > Changes in v4: > > - fixed ops->write not to do the final configuration release > - reordered patches > > Changes in v3: > > - fix write_init and write_complete signatures > > Changes in v2: > > - rebased against fpga/for-next > - added defines for configuration bits and delays > - added error mesage if ioremap() fails > - detailed how the configuration through CPLD is done Alan, Moritz, thanks for providing Acked-by, I was under the impression these patches would be taken by you through the FPGA tree, since Hartley acked the EP93xx part and since that was the tree used as a baseline. Let me know how you want to proceed, since EP93xx is not as active as other ARM SoCs, there may not be a specific tree where to stage these patches (unless you take them). Thanks! -- Florian
[PATCH v4 0/2] FPGA: TS-7300 FPGA manager
Hi all, This patch series adds support for loading bitstreams into the Altera Cyclone II connected to an EP9302 on a TS-7300 board. Changes in v4: - fixed ops->write not to do the final configuration release - reordered patches Changes in v3: - fix write_init and write_complete signatures Changes in v2: - rebased against fpga/for-next - added defines for configuration bits and delays - added error mesage if ioremap() fails - detailed how the configuration through CPLD is done Florian Fainelli (2): FPGA: Add TS-7300 FPGA manager ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300 arch/arm/mach-ep93xx/ts72xx.c | 26 +++ drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/ts73xx-fpga.c| 163 ++ 4 files changed, 197 insertions(+) create mode 100644 drivers/fpga/ts73xx-fpga.c -- 2.9.3
[PATCH v4 0/2] FPGA: TS-7300 FPGA manager
Hi all, This patch series adds support for loading bitstreams into the Altera Cyclone II connected to an EP9302 on a TS-7300 board. Changes in v4: - fixed ops->write not to do the final configuration release - reordered patches Changes in v3: - fix write_init and write_complete signatures Changes in v2: - rebased against fpga/for-next - added defines for configuration bits and delays - added error mesage if ioremap() fails - detailed how the configuration through CPLD is done Florian Fainelli (2): FPGA: Add TS-7300 FPGA manager ARM: ep93xx: Register ts73xx-fpga manager driver for TS-7300 arch/arm/mach-ep93xx/ts72xx.c | 26 +++ drivers/fpga/Kconfig | 7 ++ drivers/fpga/Makefile | 1 + drivers/fpga/ts73xx-fpga.c| 163 ++ 4 files changed, 197 insertions(+) create mode 100644 drivers/fpga/ts73xx-fpga.c -- 2.9.3
