Re: [PATCH v4 07/16] phy: qcom-qusb2: Add support for different register layouts
On Wed, Jan 3, 2018 at 4:58 PM, Manu Gautam wrote:
> New version of QUSB2 PHY has some registers offset changed.
> Add support to have register layout for a target and update
> the same in phy_configuration.
>
> Signed-off-by: Manu Gautam
> ---
LGTM.
Reviewed-by: Vivek Gautam
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 149
> +-
> 1 file changed, 109 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index 4a5b2a1..b65635f 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> @@ -37,17 +37,10 @@
> #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
> #define QUSB2PHY_PLL_PWR_CTRL 0x18
>
> -#define QUSB2PHY_PLL_STATUS0x38
> +/* QUSB2PHY_PLL_STATUS register bits */
> #define PLL_LOCKED BIT(5)
>
> -#define QUSB2PHY_PORT_TUNE10x80
> -#define QUSB2PHY_PORT_TUNE20x84
> -#define QUSB2PHY_PORT_TUNE30x88
> -#define QUSB2PHY_PORT_TUNE40x8c
> -#define QUSB2PHY_PORT_TUNE50x90
> -#define QUSB2PHY_PORT_TEST20x9c
> -
> -#define QUSB2PHY_PORT_POWERDOWN0xb4
> +/* QUSB2PHY_PORT_POWERDOWN register bits */
> #define CLAMP_N_EN BIT(5)
> #define FREEZIO_N BIT(1)
> #define POWER_DOWN BIT(0)
> @@ -59,6 +52,11 @@
> struct qusb2_phy_init_tbl {
> unsigned int offset;
> unsigned int val;
> + /*
> +* register part of layout ?
> +* if yes, then offset gives index in the reg-layout
> +*/
> + int in_layout;
> };
>
> #define QUSB2_PHY_INIT_CFG(o, v) \
> @@ -67,15 +65,50 @@ struct qusb2_phy_init_tbl {
> .val = v, \
> }
>
> +#define QUSB2_PHY_INIT_CFG_L(o, v) \
> + { \
> + .offset = o,\
> + .val = v, \
> + .in_layout = 1, \
> + }
> +
> +/* set of registers with offsets different per-PHY */
> +enum qusb2phy_reg_layout {
> + QUSB2PHY_PLL_STATUS,
> + QUSB2PHY_PORT_TUNE1,
> + QUSB2PHY_PORT_TUNE2,
> + QUSB2PHY_PORT_TUNE3,
> + QUSB2PHY_PORT_TUNE4,
> + QUSB2PHY_PORT_TUNE5,
> + QUSB2PHY_PORT_TEST1,
> + QUSB2PHY_PORT_TEST2,
> + QUSB2PHY_PORT_POWERDOWN,
> + QUSB2PHY_INTR_CTRL,
> +};
> +
> +static const unsigned int msm8996_regs_layout[] = {
> + [QUSB2PHY_PLL_STATUS] = 0x38,
> + [QUSB2PHY_PORT_TUNE1] = 0x80,
> + [QUSB2PHY_PORT_TUNE2] = 0x84,
> + [QUSB2PHY_PORT_TUNE3] = 0x88,
> + [QUSB2PHY_PORT_TUNE4] = 0x8c,
> + [QUSB2PHY_PORT_TUNE5] = 0x90,
> + [QUSB2PHY_PORT_TEST2] = 0x9c,
> + [QUSB2PHY_PORT_POWERDOWN] = 0xb4,
> +};
> +
> static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
> - QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE1, 0xf8),
> - QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE2, 0xb3),
> - QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE3, 0x83),
> - QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE4, 0xc0),
> + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
> + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
> + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
> + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
> +
> QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
> QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
> QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
> - QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TEST2, 0x14),
> +
> + QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
> +
> QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
> QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
> };
> @@ -86,11 +119,27 @@ struct qusb2_phy_cfg {
> unsigned int tbl_num;
> /* offset to PHY_CLK_SCHEME register in TCSR map */
> unsigned int clk_scheme_offset;
> +
> + /* array of registers with different offsets */
> + const unsigned int *regs;
> + unsigned int mask_core_ready;
> + unsigned int disable_ctrl;
> +
> + /* true if PHY has PLL_TEST register to select clk_scheme */
> + bool has_pll_test;
> +
> + /* true if TUNE1 register must be updated by fused value, else TUNE2
> */
> + bool update_tune1_with_efuse;
> };
>
> static const struct qusb2_phy_cfg msm8996_phy_cfg = {
> - .tbl = msm8996_init_tbl,
> - .tbl_num = ARRAY_SIZE(msm8996_init_tbl),
> + .tbl= msm8996_init_tbl,
> + .tbl_num= ARRAY_SIZE(msm8996_init_tbl),
> + .regs = msm8996_regs_layout,
> +
> + .has_pll_test = true,
> + .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
> + .mask_core_ready = PLL_LOCKED,
> };
>
> static const char * const qusb2_phy_vreg_names[] = {
> @@ -160,26
[PATCH v4 07/16] phy: qcom-qusb2: Add support for different register layouts
New version of QUSB2 PHY has some registers offset changed.
Add support to have register layout for a target and update
the same in phy_configuration.
Signed-off-by: Manu Gautam
---
drivers/phy/qualcomm/phy-qcom-qusb2.c | 149 +-
1 file changed, 109 insertions(+), 40 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c
b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 4a5b2a1..b65635f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -37,17 +37,10 @@
#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
#define QUSB2PHY_PLL_PWR_CTRL 0x18
-#define QUSB2PHY_PLL_STATUS0x38
+/* QUSB2PHY_PLL_STATUS register bits */
#define PLL_LOCKED BIT(5)
-#define QUSB2PHY_PORT_TUNE10x80
-#define QUSB2PHY_PORT_TUNE20x84
-#define QUSB2PHY_PORT_TUNE30x88
-#define QUSB2PHY_PORT_TUNE40x8c
-#define QUSB2PHY_PORT_TUNE50x90
-#define QUSB2PHY_PORT_TEST20x9c
-
-#define QUSB2PHY_PORT_POWERDOWN0xb4
+/* QUSB2PHY_PORT_POWERDOWN register bits */
#define CLAMP_N_EN BIT(5)
#define FREEZIO_N BIT(1)
#define POWER_DOWN BIT(0)
@@ -59,6 +52,11 @@
struct qusb2_phy_init_tbl {
unsigned int offset;
unsigned int val;
+ /*
+* register part of layout ?
+* if yes, then offset gives index in the reg-layout
+*/
+ int in_layout;
};
#define QUSB2_PHY_INIT_CFG(o, v) \
@@ -67,15 +65,50 @@ struct qusb2_phy_init_tbl {
.val = v, \
}
+#define QUSB2_PHY_INIT_CFG_L(o, v) \
+ { \
+ .offset = o,\
+ .val = v, \
+ .in_layout = 1, \
+ }
+
+/* set of registers with offsets different per-PHY */
+enum qusb2phy_reg_layout {
+ QUSB2PHY_PLL_STATUS,
+ QUSB2PHY_PORT_TUNE1,
+ QUSB2PHY_PORT_TUNE2,
+ QUSB2PHY_PORT_TUNE3,
+ QUSB2PHY_PORT_TUNE4,
+ QUSB2PHY_PORT_TUNE5,
+ QUSB2PHY_PORT_TEST1,
+ QUSB2PHY_PORT_TEST2,
+ QUSB2PHY_PORT_POWERDOWN,
+ QUSB2PHY_INTR_CTRL,
+};
+
+static const unsigned int msm8996_regs_layout[] = {
+ [QUSB2PHY_PLL_STATUS] = 0x38,
+ [QUSB2PHY_PORT_TUNE1] = 0x80,
+ [QUSB2PHY_PORT_TUNE2] = 0x84,
+ [QUSB2PHY_PORT_TUNE3] = 0x88,
+ [QUSB2PHY_PORT_TUNE4] = 0x8c,
+ [QUSB2PHY_PORT_TUNE5] = 0x90,
+ [QUSB2PHY_PORT_TEST2] = 0x9c,
+ [QUSB2PHY_PORT_POWERDOWN] = 0xb4,
+};
+
static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
- QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE1, 0xf8),
- QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE2, 0xb3),
- QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE3, 0x83),
- QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE4, 0xc0),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
+
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
- QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TEST2, 0x14),
+
+ QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
+
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
};
@@ -86,11 +119,27 @@ struct qusb2_phy_cfg {
unsigned int tbl_num;
/* offset to PHY_CLK_SCHEME register in TCSR map */
unsigned int clk_scheme_offset;
+
+ /* array of registers with different offsets */
+ const unsigned int *regs;
+ unsigned int mask_core_ready;
+ unsigned int disable_ctrl;
+
+ /* true if PHY has PLL_TEST register to select clk_scheme */
+ bool has_pll_test;
+
+ /* true if TUNE1 register must be updated by fused value, else TUNE2 */
+ bool update_tune1_with_efuse;
};
static const struct qusb2_phy_cfg msm8996_phy_cfg = {
- .tbl = msm8996_init_tbl,
- .tbl_num = ARRAY_SIZE(msm8996_init_tbl),
+ .tbl= msm8996_init_tbl,
+ .tbl_num= ARRAY_SIZE(msm8996_init_tbl),
+ .regs = msm8996_regs_layout,
+
+ .has_pll_test = true,
+ .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
+ .mask_core_ready = PLL_LOCKED,
};
static const char * const qusb2_phy_vreg_names[] = {
@@ -160,26 +209,32 @@ static inline void qusb2_clrbits(void __iomem *base, u32
offset, u32 val)
static inline
void qcom_qusb2_phy_configure(void __iomem *base,
+ const unsigned int *regs,
const struct qusb2_phy_init_tbl tbl[], int num)
{
int i;
- for (i = 0; i < num; i++)
-
