[PATCH v4 08/11] arm64: dts: allwinner: a64: Add display pipeline
From: Jagan Teki
Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
TCON is connected to LCD and the second is to HDMI.
The HDMI controller/PHY pair is similar to the one on H3/H5.
Add all required device tree nodes of the display pipeline, including
the TCON0 LCD one and the TCON1 HDMI one.
Signed-off-by: Jagan Teki
[Icenowy: refactor commit message and add 1st pipeline]
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- Misc fixes
- Dropped second PLL from HDMI PHY clock
Changes for v3.1:
- Refactor commit message to make it more clear.
- Added first pipeline (mixer0 -> tcon0)
Changes for v3:
- Squash all pipeline components in one patch
- Add status for mixer1 and tcon1
Changes for v2:
- Change compatibles and other based on previous patch changes
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 170 ++
1 file changed, 170 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index b73f9287c3f0..8c7bcae0b8ec 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -121,6 +121,13 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun50i-a64-display-engine";
+ allwinner,pipelines = <>,
+ <>;
+ status = "disabled";
+ };
+
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -203,6 +210,52 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ mixer0: mixer@10 {
+ compatible = "allwinner,sun50i-a64-de2-mixer-0";
+ reg = <0x10 0x10>;
+ clocks = <_clocks CLK_BUS_MIXER0>,
+<_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint {
+ remote-endpoint =
<_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer@20 {
+ compatible = "allwinner,sun50i-a64-de2-mixer-1";
+ reg = <0x20 0x10>;
+ clocks = <_clocks CLK_BUS_MIXER1>,
+<_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <_clocks RST_MIXER1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ reg = <1>;
+
+ mixer1_out_tcon1: endpoint {
+ remote-endpoint =
<_in_mixer1>;
+ };
+ };
+ };
+ };
};
syscon: syscon@1c0 {
@@ -237,6 +290,75 @@
#dma-cells = <1>;
};
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun50i-a64-tcon-lcd",
+"allwinner,sun8i-a83t-tcon-lcd";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_TCON0>, < CLK_TCON0>;
+ clock-names = "ahb", "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = < RST_BUS_TCON0>, < RST_BUS_LVDS>;
+ reset-names = "lcd", "lvds";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+
[PATCH v4 08/11] arm64: dts: allwinner: a64: Add display pipeline
From: Jagan Teki
Allwinner A64 have a display pipeline with 2 mixers/TCONs, the first
TCON is connected to LCD and the second is to HDMI.
The HDMI controller/PHY pair is similar to the one on H3/H5.
Add all required device tree nodes of the display pipeline, including
the TCON0 LCD one and the TCON1 HDMI one.
Signed-off-by: Jagan Teki
[Icenowy: refactor commit message and add 1st pipeline]
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- Misc fixes
- Dropped second PLL from HDMI PHY clock
Changes for v3.1:
- Refactor commit message to make it more clear.
- Added first pipeline (mixer0 -> tcon0)
Changes for v3:
- Squash all pipeline components in one patch
- Add status for mixer1 and tcon1
Changes for v2:
- Change compatibles and other based on previous patch changes
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 170 ++
1 file changed, 170 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index b73f9287c3f0..8c7bcae0b8ec 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -121,6 +121,13 @@
};
};
+ de: display-engine {
+ compatible = "allwinner,sun50i-a64-display-engine";
+ allwinner,pipelines = <>,
+ <>;
+ status = "disabled";
+ };
+
osc24M: osc24M_clk {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -203,6 +210,52 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+
+ mixer0: mixer@10 {
+ compatible = "allwinner,sun50i-a64-de2-mixer-0";
+ reg = <0x10 0x10>;
+ clocks = <_clocks CLK_BUS_MIXER0>,
+<_clocks CLK_MIXER0>;
+ clock-names = "bus",
+ "mod";
+ resets = <_clocks RST_MIXER0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer0_out: port@1 {
+ reg = <1>;
+
+ mixer0_out_tcon0: endpoint {
+ remote-endpoint =
<_in_mixer0>;
+ };
+ };
+ };
+ };
+
+ mixer1: mixer@20 {
+ compatible = "allwinner,sun50i-a64-de2-mixer-1";
+ reg = <0x20 0x10>;
+ clocks = <_clocks CLK_BUS_MIXER1>,
+<_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <_clocks RST_MIXER1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port@1 {
+ reg = <1>;
+
+ mixer1_out_tcon1: endpoint {
+ remote-endpoint =
<_in_mixer1>;
+ };
+ };
+ };
+ };
};
syscon: syscon@1c0 {
@@ -237,6 +290,75 @@
#dma-cells = <1>;
};
+ tcon0: lcd-controller@1c0c000 {
+ compatible = "allwinner,sun50i-a64-tcon-lcd",
+"allwinner,sun8i-a83t-tcon-lcd";
+ reg = <0x01c0c000 0x1000>;
+ interrupts = ;
+ clocks = < CLK_BUS_TCON0>, < CLK_TCON0>;
+ clock-names = "ahb", "tcon-ch0";
+ clock-output-names = "tcon-pixel-clock";
+ resets = < RST_BUS_TCON0>, < RST_BUS_LVDS>;
+ reset-names = "lcd", "lvds";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon0_in: port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+
