Re: [PATCH v4 1/2] clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver
On Thu, Oct 17, 2019 at 5:16 PM Jeffrey Hugo wrote:
>
> On Thu, Oct 17, 2019 at 3:50 PM Stephen Boyd wrote:
> >
> > Quoting Jeffrey Hugo (2019-10-01 18:16:40)
> > > +static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
> > > + F(18000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > + F(25700, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > + F(34200, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > + F(41400, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > + F(51500, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > + F(59600, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > + F(67000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > + F(71000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > > + { }
> >
> > I guess this one doesn't do PLL ping pong? Instead we just reprogram the
> > PLL all the time? Can we have rcg2 clk ops that set the rate on the
> > parent to be exactly twice as much as the incoming frequency? I thought
> > we already had this support in the code. Indeed, it is part of
> > _freq_tbl_determine_rate() in clk-rcg.c, but not yet implemented in the
> > same function name in clk-rcg2.c! Can you implement it? That way we
> > don't need this long frequency table, just this weird one where it looks
> > like:
> >
> > { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }
> > { }
> >
> > And then some more logic in the rcg2 ops to allow this possibility for a
> > frequency table when CLK_SET_RATE_PARENT is set.
>
> Does not do PLL ping pong. I'll look at extending the rcg2 ops like
> you describe.
Am I missing something? From what I can tell, what you describe is
not implemented.
The only in-tree example of a freq_tbl with only a src and a pre_div
defined for rcg ops is for the tv_src clk in mmcc-msm8960 [1]
However, that uses a variant of rcg ops, clk_rcg_bypass_ops, not clk_rcg_ops.
clk_rcg_bypass_ops has its own determine_rate implementation which
does not utilize _freq_tbl_determine_rate(), and can only do a 1:1
input rate to output ratio (we want a 1:2).
_freq_tbl_determine_rate() in either rcg_ops or rcg2_ops won't work,
because they both use qcom_find_freq() which doesn't work when your
table doesn't specify any frequencies (f->freq is 0).
qcom_find_freq() won't iterate through the table, therefore f in
qcom_find_freq() won't be pointing at the end of the table (the null
entry), so when qcom_find_freq decrements f in the return, it actually
goes off the beginning of the array in an array out of bounds
violation.
Please advise how you would like to proceed.
I can still extend rcg2_ops to do what you want, but it won't be based
on what rcg_ops is doing.
I can spin a rcg2_ops variant to do what you want, with a custom
determine_rate, but it doesn't seem like I'll really be saving any
lines of code. Whatever I eliminate by minimizing the gfx3d
freq_table I will surely be putting into clk-rcg2.c
Or, I can just drop this idea and keep the freq_tbl as it is. Seems
like just a one off scenario.
[1] -
https://elixir.bootlin.com/linux/v5.4-rc2/source/drivers/clk/qcom/mmcc-msm8960.c#L1416
Re: [PATCH v4 1/2] clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver
On Thu, Oct 17, 2019 at 10:11 PM Taniya Das wrote:
>
> Hi Jeffrey,
>
> On 10/2/2019 6:46 AM, Jeffrey Hugo wrote:
> > The GPUCC manages the clocks for the Adreno GPU found on MSM8998.
> >
> > Signed-off-by: Jeffrey Hugo
> > ---
> > drivers/clk/qcom/Kconfig | 9 +
> > drivers/clk/qcom/Makefile| 1 +
> > drivers/clk/qcom/gpucc-msm8998.c | 346 +++
> > 3 files changed, 356 insertions(+)
> > create mode 100644 drivers/clk/qcom/gpucc-msm8998.c
> >
> > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> > index 96efee18fa6c..31a70168327c 100644
> > --- a/drivers/clk/qcom/Kconfig
> > +++ b/drivers/clk/qcom/Kconfig
> > @@ -230,6 +230,15 @@ config MSM_MMCC_8998
> > Say Y if you want to support multimedia devices such as display,
> > graphics, video encode/decode, camera, etc.
> >
> > +config MSM_GPUCC_8998
> > + tristate "MSM8998 Graphics Clock Controller"
> > + select MSM_GCC_8998
> > + select QCOM_GDSC
> > + help
> > + Support for the graphics clock controller on MSM8998 devices.
> > + Say Y if you want to support graphics controller devices and
> > + functionality such as 3D graphics.
> > +
> > config QCS_GCC_404
> > tristate "QCS404 Global Clock Controller"
> > help
> > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> > index 0ac3c1459313..616b68f91db6 100644
> > --- a/drivers/clk/qcom/Makefile
> > +++ b/drivers/clk/qcom/Makefile
> > @@ -33,6 +33,7 @@ obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
> > obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
> > obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
> > obj-$(CONFIG_MSM_GCC_8998) += gcc-msm8998.o
> > +obj-$(CONFIG_MSM_GPUCC_8998) += gpucc-msm8998.o
> > obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
> > obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
> > obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
> > diff --git a/drivers/clk/qcom/gpucc-msm8998.c
> > b/drivers/clk/qcom/gpucc-msm8998.c
> > new file mode 100644
> > index ..f0ccb4963885
> > --- /dev/null
> > +++ b/drivers/clk/qcom/gpucc-msm8998.c
> > @@ -0,0 +1,346 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2019, Jeffrey Hugo
> > + */
> > +
>
> Copyright (c) 2019, The Linux Foundation. All rights reserved.
No, what I have is correct. I'll send you the resources regarding
this issue since its not really relevant to the community.
>
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +
> > +#include
> > +
> > +#include "common.h"
> > +#include "clk-regmap.h"
> > +#include "clk-regmap-divider.h"
> > +#include "clk-alpha-pll.h"
> > +#include "clk-rcg.h"
> > +#include "clk-branch.h"
> > +#include "reset.h"
> > +#include "gdsc.h"
> > +
> > +enum {
> > + P_XO,
> > + P_GPLL0,
> > + P_GPUPLL0_OUT_EVEN,
> > +};
> > +
> > +/* Instead of going directly to the block, XO is routed through this
> > branch */
> > +static struct clk_branch gpucc_cxo_clk = {
> > + .halt_reg = 0x1020,
> > + .clkr = {
> > + .enable_reg = 0x1020,
> > + .enable_mask = BIT(0),
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gpucc_cxo_clk",
> > + .parent_data = &(const struct clk_parent_data){
> > + .fw_name = "xo",
> > + .name = "xo"
> > + },
> > + .num_parents = 1,
> > + .ops = _branch2_ops,
> > + .flags = CLK_IS_CRITICAL,
> > + },
> > + },
> > +};
> > +
> > +static const struct clk_div_table post_div_table_fabia_even[] = {
> > + { 0x0, 1 },
> > + { 0x1, 2 },
> > + { 0x3, 4 },
> > + { 0x7, 8 },
> > + { }
> > +};
> > +
> > +static struct clk_alpha_pll gpupll0 = {
> > + .offset = 0x0,
> > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
> > + .clkr.hw.init = &(struct clk_init_data){
> > + .name = "gpupll0",
> > + .parent_hws = (const struct clk_hw *[]){
> > _cxo_clk.clkr.hw },
> > + .num_parents = 1,
> > + .ops = _alpha_pll_fixed_fabia_ops,
> > + },
> > +};
> > +
> > +static struct clk_alpha_pll_postdiv gpupll0_out_even = {
> > + .offset = 0x0,
> > + .post_div_shift = 8,
> > + .post_div_table = post_div_table_fabia_even,
> > + .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
> > + .width = 4,
> > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
> > + .clkr.hw.init = &(struct clk_init_data){
> > + .name = "gpupll0_out_even",
> > + .parent_hws = (const struct clk_hw *[]){ },
> > + .num_parents = 1,
> > + .ops = _alpha_pll_postdiv_fabia_ops,
> > + },
> > +};
> > +
> > +static const struct parent_map
Re: [PATCH v4 1/2] clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver
Hi Jeffrey,
On 10/2/2019 6:46 AM, Jeffrey Hugo wrote:
The GPUCC manages the clocks for the Adreno GPU found on MSM8998.
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/gpucc-msm8998.c | 346 +++
3 files changed, 356 insertions(+)
create mode 100644 drivers/clk/qcom/gpucc-msm8998.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 96efee18fa6c..31a70168327c 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -230,6 +230,15 @@ config MSM_MMCC_8998
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+config MSM_GPUCC_8998
+ tristate "MSM8998 Graphics Clock Controller"
+ select MSM_GCC_8998
+ select QCOM_GDSC
+ help
+ Support for the graphics clock controller on MSM8998 devices.
+ Say Y if you want to support graphics controller devices and
+ functionality such as 3D graphics.
+
config QCS_GCC_404
tristate "QCS404 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 0ac3c1459313..616b68f91db6 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
obj-$(CONFIG_MSM_GCC_8998) += gcc-msm8998.o
+obj-$(CONFIG_MSM_GPUCC_8998) += gpucc-msm8998.o
obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c
new file mode 100644
index ..f0ccb4963885
--- /dev/null
+++ b/drivers/clk/qcom/gpucc-msm8998.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Jeffrey Hugo
+ */
+
Copyright (c) 2019, The Linux Foundation. All rights reserved.
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+#include "gdsc.h"
+
+enum {
+ P_XO,
+ P_GPLL0,
+ P_GPUPLL0_OUT_EVEN,
+};
+
+/* Instead of going directly to the block, XO is routed through this branch */
+static struct clk_branch gpucc_cxo_clk = {
+ .halt_reg = 0x1020,
+ .clkr = {
+ .enable_reg = 0x1020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpucc_cxo_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ .name = "xo"
+ },
+ .num_parents = 1,
+ .ops = _branch2_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_fabia_even[] = {
+ { 0x0, 1 },
+ { 0x1, 2 },
+ { 0x3, 4 },
+ { 0x7, 8 },
+ { }
+};
+
+static struct clk_alpha_pll gpupll0 = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpupll0",
+ .parent_hws = (const struct clk_hw *[]){ _cxo_clk.clkr.hw
},
+ .num_parents = 1,
+ .ops = _alpha_pll_fixed_fabia_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpupll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_fabia_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpupll0_out_even",
+ .parent_hws = (const struct clk_hw *[]){ },
+ .num_parents = 1,
+ .ops = _alpha_pll_postdiv_fabia_ops,
+ },
+};
+
+static const struct parent_map gpu_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 5 },
+};
+
+static const struct clk_parent_data gpu_xo_gpll0[] = {
+ { .hw = _cxo_clk.clkr.hw },
+ { .fw_name = "gpll0", .name = "gpll0" },
+};
+
+static const struct parent_map gpu_xo_gpupll0_map[] = {
+ { P_XO, 0 },
+ { P_GPUPLL0_OUT_EVEN, 1 },
+};
+
+static const struct clk_parent_data gpu_xo_gpupll0[] = {
+ { .hw = _cxo_clk.clkr.hw },
+ { .hw = _out_even.clkr.hw },
+};
+
+static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
+ F(1920, P_XO, 1, 0, 0),
+ F(5000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static
Re: [PATCH v4 1/2] clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver
On Thu, Oct 17, 2019 at 3:50 PM Stephen Boyd wrote:
>
> Quoting Jeffrey Hugo (2019-10-01 18:16:40)
> > diff --git a/drivers/clk/qcom/gpucc-msm8998.c
> > b/drivers/clk/qcom/gpucc-msm8998.c
> > new file mode 100644
> > index ..f0ccb4963885
> > --- /dev/null
> > +++ b/drivers/clk/qcom/gpucc-msm8998.c
> > @@ -0,0 +1,346 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2019, Jeffrey Hugo
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
> Drop this include please.
Will do.
>
> > +
> > +
> > +static struct clk_rcg2 rbcpr_clk_src = {
> > + .cmd_rcgr = 0x1030,
> > + .hid_width = 5,
> > + .parent_map = gpu_xo_gpll0_map,
> > + .freq_tbl = ftbl_rbcpr_clk_src,
> > + .clkr.hw.init = &(struct clk_init_data){
> > + .name = "rbcpr_clk_src",
> > + .parent_data = gpu_xo_gpll0,
> > + .num_parents = 2,
> > + .ops = _rcg2_ops,
> > + },
> > +};
> > +
> > +static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
> > + F(18000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > + F(25700, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > + F(34200, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > + F(41400, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > + F(51500, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > + F(59600, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > + F(67000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > + F(71000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> > + { }
>
> I guess this one doesn't do PLL ping pong? Instead we just reprogram the
> PLL all the time? Can we have rcg2 clk ops that set the rate on the
> parent to be exactly twice as much as the incoming frequency? I thought
> we already had this support in the code. Indeed, it is part of
> _freq_tbl_determine_rate() in clk-rcg.c, but not yet implemented in the
> same function name in clk-rcg2.c! Can you implement it? That way we
> don't need this long frequency table, just this weird one where it looks
> like:
>
> { .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }
> { }
>
> And then some more logic in the rcg2 ops to allow this possibility for a
> frequency table when CLK_SET_RATE_PARENT is set.
Does not do PLL ping pong. I'll look at extending the rcg2 ops like
you describe.
>
> > +};
> > +
> > +static struct clk_rcg2 gfx3d_clk_src = {
> > + .cmd_rcgr = 0x1070,
> > + .hid_width = 5,
> > + .parent_map = gpu_xo_gpupll0_map,
> > + .freq_tbl = ftbl_gfx3d_clk_src,
> > + .clkr.hw.init = &(struct clk_init_data){
> > + .name = "gfx3d_clk_src",
> > + .parent_data = gpu_xo_gpupll0,
> > + .num_parents = 2,
> > + .ops = _rcg2_ops,
> > + .flags = CLK_OPS_PARENT_ENABLE,
>
> Needs CLK_SET_RATE_PARENT presumably?
Ah yeah. Thanks for catching.
>
> > + },
> > +};
> > +
> > +static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
> > + F(1920, P_XO, 1, 0, 0),
> > + { }
> > +};
> > +
> [...]
> > +
> > +static const struct qcom_cc_desc gpucc_msm8998_desc = {
> > + .config = _msm8998_regmap_config,
> > + .clks = gpucc_msm8998_clocks,
> > + .num_clks = ARRAY_SIZE(gpucc_msm8998_clocks),
> > + .resets = gpucc_msm8998_resets,
> > + .num_resets = ARRAY_SIZE(gpucc_msm8998_resets),
> > + .gdscs = gpucc_msm8998_gdscs,
> > + .num_gdscs = ARRAY_SIZE(gpucc_msm8998_gdscs),
> > +};
> > +
> > +static const struct of_device_id gpucc_msm8998_match_table[] = {
> > + { .compatible = "qcom,gpucc-msm8998" },
>
> The compatible is different. In the merged binding it is
> qcom,msm8998-gpucc. Either fix this or fix the binding please.
This is wrong. Will fix.
Re: [PATCH v4 1/2] clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver
Quoting Jeffrey Hugo (2019-10-01 18:16:40)
> diff --git a/drivers/clk/qcom/gpucc-msm8998.c
> b/drivers/clk/qcom/gpucc-msm8998.c
> new file mode 100644
> index ..f0ccb4963885
> --- /dev/null
> +++ b/drivers/clk/qcom/gpucc-msm8998.c
> @@ -0,0 +1,346 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019, Jeffrey Hugo
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
Drop this include please.
> +
> +
> +static struct clk_rcg2 rbcpr_clk_src = {
> + .cmd_rcgr = 0x1030,
> + .hid_width = 5,
> + .parent_map = gpu_xo_gpll0_map,
> + .freq_tbl = ftbl_rbcpr_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "rbcpr_clk_src",
> + .parent_data = gpu_xo_gpll0,
> + .num_parents = 2,
> + .ops = _rcg2_ops,
> + },
> +};
> +
> +static const struct freq_tbl ftbl_gfx3d_clk_src[] = {
> + F(18000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> + F(25700, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> + F(34200, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> + F(41400, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> + F(51500, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> + F(59600, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> + F(67000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> + F(71000, P_GPUPLL0_OUT_EVEN, 2, 0, 0),
> + { }
I guess this one doesn't do PLL ping pong? Instead we just reprogram the
PLL all the time? Can we have rcg2 clk ops that set the rate on the
parent to be exactly twice as much as the incoming frequency? I thought
we already had this support in the code. Indeed, it is part of
_freq_tbl_determine_rate() in clk-rcg.c, but not yet implemented in the
same function name in clk-rcg2.c! Can you implement it? That way we
don't need this long frequency table, just this weird one where it looks
like:
{ .src = P_GPUPLL0_OUT_EVEN, .pre_div = 3 }
{ }
And then some more logic in the rcg2 ops to allow this possibility for a
frequency table when CLK_SET_RATE_PARENT is set.
> +};
> +
> +static struct clk_rcg2 gfx3d_clk_src = {
> + .cmd_rcgr = 0x1070,
> + .hid_width = 5,
> + .parent_map = gpu_xo_gpupll0_map,
> + .freq_tbl = ftbl_gfx3d_clk_src,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gfx3d_clk_src",
> + .parent_data = gpu_xo_gpupll0,
> + .num_parents = 2,
> + .ops = _rcg2_ops,
> + .flags = CLK_OPS_PARENT_ENABLE,
Needs CLK_SET_RATE_PARENT presumably?
> + },
> +};
> +
> +static const struct freq_tbl ftbl_rbbmtimer_clk_src[] = {
> + F(1920, P_XO, 1, 0, 0),
> + { }
> +};
> +
[...]
> +
> +static const struct qcom_cc_desc gpucc_msm8998_desc = {
> + .config = _msm8998_regmap_config,
> + .clks = gpucc_msm8998_clocks,
> + .num_clks = ARRAY_SIZE(gpucc_msm8998_clocks),
> + .resets = gpucc_msm8998_resets,
> + .num_resets = ARRAY_SIZE(gpucc_msm8998_resets),
> + .gdscs = gpucc_msm8998_gdscs,
> + .num_gdscs = ARRAY_SIZE(gpucc_msm8998_gdscs),
> +};
> +
> +static const struct of_device_id gpucc_msm8998_match_table[] = {
> + { .compatible = "qcom,gpucc-msm8998" },
The compatible is different. In the merged binding it is
qcom,msm8998-gpucc. Either fix this or fix the binding please.
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, gpucc_msm8998_match_table);
> +
[PATCH v4 1/2] clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver
The GPUCC manages the clocks for the Adreno GPU found on MSM8998.
Signed-off-by: Jeffrey Hugo
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile| 1 +
drivers/clk/qcom/gpucc-msm8998.c | 346 +++
3 files changed, 356 insertions(+)
create mode 100644 drivers/clk/qcom/gpucc-msm8998.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 96efee18fa6c..31a70168327c 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -230,6 +230,15 @@ config MSM_MMCC_8998
Say Y if you want to support multimedia devices such as display,
graphics, video encode/decode, camera, etc.
+config MSM_GPUCC_8998
+ tristate "MSM8998 Graphics Clock Controller"
+ select MSM_GCC_8998
+ select QCOM_GDSC
+ help
+ Support for the graphics clock controller on MSM8998 devices.
+ Say Y if you want to support graphics controller devices and
+ functionality such as 3D graphics.
+
config QCS_GCC_404
tristate "QCS404 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 0ac3c1459313..616b68f91db6 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_MSM_GCC_8994) += gcc-msm8994.o
obj-$(CONFIG_MSM_GCC_8996) += gcc-msm8996.o
obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
obj-$(CONFIG_MSM_GCC_8998) += gcc-msm8998.o
+obj-$(CONFIG_MSM_GPUCC_8998) += gpucc-msm8998.o
obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c
new file mode 100644
index ..f0ccb4963885
--- /dev/null
+++ b/drivers/clk/qcom/gpucc-msm8998.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Jeffrey Hugo
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-alpha-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "reset.h"
+#include "gdsc.h"
+
+enum {
+ P_XO,
+ P_GPLL0,
+ P_GPUPLL0_OUT_EVEN,
+};
+
+/* Instead of going directly to the block, XO is routed through this branch */
+static struct clk_branch gpucc_cxo_clk = {
+ .halt_reg = 0x1020,
+ .clkr = {
+ .enable_reg = 0x1020,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpucc_cxo_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "xo",
+ .name = "xo"
+ },
+ .num_parents = 1,
+ .ops = _branch2_ops,
+ .flags = CLK_IS_CRITICAL,
+ },
+ },
+};
+
+static const struct clk_div_table post_div_table_fabia_even[] = {
+ { 0x0, 1 },
+ { 0x1, 2 },
+ { 0x3, 4 },
+ { 0x7, 8 },
+ { }
+};
+
+static struct clk_alpha_pll gpupll0 = {
+ .offset = 0x0,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpupll0",
+ .parent_hws = (const struct clk_hw *[]){ _cxo_clk.clkr.hw
},
+ .num_parents = 1,
+ .ops = _alpha_pll_fixed_fabia_ops,
+ },
+};
+
+static struct clk_alpha_pll_postdiv gpupll0_out_even = {
+ .offset = 0x0,
+ .post_div_shift = 8,
+ .post_div_table = post_div_table_fabia_even,
+ .num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
+ .width = 4,
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpupll0_out_even",
+ .parent_hws = (const struct clk_hw *[]){ },
+ .num_parents = 1,
+ .ops = _alpha_pll_postdiv_fabia_ops,
+ },
+};
+
+static const struct parent_map gpu_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 5 },
+};
+
+static const struct clk_parent_data gpu_xo_gpll0[] = {
+ { .hw = _cxo_clk.clkr.hw },
+ { .fw_name = "gpll0", .name = "gpll0" },
+};
+
+static const struct parent_map gpu_xo_gpupll0_map[] = {
+ { P_XO, 0 },
+ { P_GPUPLL0_OUT_EVEN, 1 },
+};
+
+static const struct clk_parent_data gpu_xo_gpupll0[] = {
+ { .hw = _cxo_clk.clkr.hw },
+ { .hw = _out_even.clkr.hw },
+};
+
+static const struct freq_tbl ftbl_rbcpr_clk_src[] = {
+ F(1920, P_XO, 1, 0, 0),
+ F(5000, P_GPLL0, 12, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 rbcpr_clk_src = {
+ .cmd_rcgr = 0x1030,
+ .hid_width = 5,
+ .parent_map = gpu_xo_gpll0_map,
+ .freq_tbl
