[PATCH v4 1/2] mtd: spi-nor: cadence-quadspi: Disable the DAC for Intel LGM SoC

[Ramuthevar,Vadivel MuruganX]

From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthe...@linux.intel.com>

On Intel Lightning Mountain(LGM) SoCs QSPI controller do not use
Direct Access Controller(DAC).

This patch adds a quirk to disable the Direct Access Controller
for data transfer instead it uses indirect data transfer.

Signed-off-by: Ramuthevar Vadivel Murugan 
<vadivel.muruganx.ramuthe...@linux.intel.com>
---
 drivers/mtd/spi-nor/Kconfig           |  2 +-
 drivers/mtd/spi-nor/cadence-quadspi.c | 33 +++++++++++++++++++++++++++------
 2 files changed, 28 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index f237fcdf7f86..ef1aa369c2e3 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -36,7 +36,7 @@ config SPI_ASPEED_SMC
 
 config SPI_CADENCE_QUADSPI
        tristate "Cadence Quad SPI controller"
-       depends on OF && (ARM || ARM64 || COMPILE_TEST)
+       depends on OF && (ARM || ARM64 || COMPILE_TEST || X86)
        help
          Enable support for the Cadence Quad SPI Flash controller.
 
diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c 
b/drivers/mtd/spi-nor/cadence-quadspi.c
index 7bef63947b29..0ad076eaa81b 100644
--- a/drivers/mtd/spi-nor/cadence-quadspi.c
+++ b/drivers/mtd/spi-nor/cadence-quadspi.c
@@ -34,6 +34,7 @@
 
 /* Quirks */
 #define CQSPI_NEEDS_WR_DELAY           BIT(0)
+#define CQSPI_DISABLE_DAC_MODE         BIT(1)
 
 /* Capabilities mask */
 #define CQSPI_BASE_HWCAPS_MASK                                 \
@@ -600,6 +601,13 @@ static int cqspi_write_setup(struct spi_nor *nor)
        struct cqspi_st *cqspi = f_pdata->cqspi;
        void __iomem *reg_base = cqspi->iobase;
 
+       /* Disable direct access controller */
+       if (!f_pdata->use_direct_mode) {
+               reg = readl(reg_base + CQSPI_REG_CONFIG);
+               reg &= ~CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
+               writel(reg, reg_base + CQSPI_REG_CONFIG);
+       }
+
        /* Set opcode. */
        reg = nor->program_opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB;
        writel(reg, reg_base + CQSPI_REG_WR_INSTR);
@@ -1292,12 +1300,16 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, 
struct device_node *np)
                f_pdata->registered = true;
 
                if (mtd->size <= cqspi->ahb_size) {
-                       f_pdata->use_direct_mode = true;
-                       dev_dbg(nor->dev, "using direct mode for %s\n",
-                               mtd->name);
-
-                       if (!cqspi->rx_chan)
-                               cqspi_request_mmap_dma(cqspi);
+                       if (ddata && (ddata->quirks & CQSPI_DISABLE_DAC_MODE)) {
+                               f_pdata->use_direct_mode = false;
+                       } else {
+                               f_pdata->use_direct_mode = true;
+                               dev_dbg(nor->dev, "using direct mode for %s\n",
+                                       mtd->name);
+
+                               if (!cqspi->rx_chan)
+                                       cqspi_request_mmap_dma(cqspi);
+                       }
                }
        }
 
@@ -1501,6 +1513,11 @@ static const struct cqspi_driver_platdata am654_ospi = {
        .quirks = CQSPI_NEEDS_WR_DELAY,
 };
 
+static const struct cqspi_driver_platdata intel_lgm_qspi = {
+       .hwcaps_mask = CQSPI_BASE_HWCAPS_MASK,
+       .quirks = CQSPI_DISABLE_DAC_MODE,
+};
+
 static const struct of_device_id cqspi_dt_ids[] = {
        {
                .compatible = "cdns,qspi-nor",
@@ -1514,6 +1531,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
                .compatible = "ti,am654-ospi",
                .data = &am654_ospi,
        },
+       {
+               .compatible = "intel,lgm-qspi",
+               .data = &intel_lgm_qspi,
+       },
        { /* end of table */ }
 };
 
-- 
2.11.0