Re: [PATCH v4 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
On Thu, 17 Aug 2017 10:30:23 +0800
Zhangshaokun wrote:
> Hi Mark,
>
> Thanks for your comments.
>
> On 2017/8/15 17:50, Mark Rutland wrote:
> > Hi,
> >
> > On Tue, Jul 25, 2017 at 08:10:37PM +0800, Shaokun Zhang wrote:
> >> This patch adds documentation for the uncore PMUs on HiSilicon SoC.
> >>
> >> Reviewed-by: Jonathan Cameron
> >> Signed-off-by: Shaokun Zhang
> >> Signed-off-by: Anurup M
> >> ---
> >> Documentation/perf/hisi-pmu.txt | 52
> >> +
> >> 1 file changed, 52 insertions(+)
> >> create mode 100644 Documentation/perf/hisi-pmu.txt
> >>
> >> diff --git a/Documentation/perf/hisi-pmu.txt
> >> b/Documentation/perf/hisi-pmu.txt
> >> new file mode 100644
> >> index 000..f45a03d
> >> --- /dev/null
> >> +++ b/Documentation/perf/hisi-pmu.txt
> >> @@ -0,0 +1,52 @@
> >> +HiSilicon SoC uncore Performance Monitoring Unit (PMU)
> >> +==
> >> +The HiSilicon SoC chip comprehends various independent system device PMUs
> >>
> >
> > Nit: s/comprehends/comprises/ would be easier to read.
> >
>
> Ok.
s/comprises/includes/ would perhaps be even better. There are a few other
things in the SoC beyond independent system device PMUs :)
(good spot though - I completely missed comprehends when doing the internal
review!)
>
> >> +such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
> >> +independent and have hardware logic to gather statistics and performance
> >> +information.
> >> +
> >> +HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
> >
> > Nit: The Hisilicon SoC
> >
>
> Ok.
I disagree. It is odd but the company name is HiSilicon with the capital S.
>
> >> +(CCL) is made up of 4 cpu cores sharing one L3 cache; Each CPU die is
> >
> > Nit: s/Each/each/
> >
>
> Ok.
>
> >> +called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
> >> +two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
> >> +
> >> +HiSilicon SoC uncore PMU driver
> >> +---
> >> +Each device PMU has separate registers for event counting, control and
> >> +interrupt, and the PMU driver shall register perf PMU drivers like L3C,
> >> +HHA and DDRC etc. The available events and configuration options shall
> >> +be described in the sysfs, see /sys/devices/hisi_*
> >
> > What exactly its exposed under /sys/devices/hisi_* ?
> >
>
> Apologies that i shall list
> /sys/devices/hisi_sccl{X}_/ and
> will change it in next version.
>
> >> or /sys/bus/
> >> +event_source/devices/hisi_*.
> >
> > Please don't wrap paths; keep this on one line.
> >
>
> Ok.
>
> >> +The "perf list" command shall list the available events from sysfs.
> >> +
> >> +Each L3C, HHA and DDRC in one SCCL are registered as an separate PMU with
> >> perf.
> >> +The PMU name will appear in event listing as hisi_module
> >> _.
> >> +where "index-id" is the index of module and "sccl-id" is the identifier of
> >> +the SCCL.
> >> +e.g. hisi_l3c0_1/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 and
> >> SCCL
> >> +ID #1.
> >> +e.g. hisi_hha0_1/rx_operations is RX_OPERATIONS event of HHA index #0 and
> >> SCCL
> >> +ID #1.
> >
> > It would make more sense for this to be hierarichal, e.g.
> > hisi_sccl{X}_l3c{Y}.
> >
>
> Surely, it is nicer.
>
> Thanks.
> Shaokun
>
> > Other than the above nits, this documentation is very useful. Thanks for
> > putting this together.
> >
> > Thanks,
> > Mark.
> > ___
> > linuxarm mailing list
> > linux...@huawei.com
> > http://rnd-openeuler.huawei.com/mailman/listinfo/linuxarm
> >
> > .
> >
>
> ___
> linuxarm mailing list
> linux...@huawei.com
> http://rnd-openeuler.huawei.com/mailman/listinfo/linuxarm
Re: [PATCH v4 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
Hi Mark,
Thanks for your comments.
On 2017/8/15 17:50, Mark Rutland wrote:
> Hi,
>
> On Tue, Jul 25, 2017 at 08:10:37PM +0800, Shaokun Zhang wrote:
>> This patch adds documentation for the uncore PMUs on HiSilicon SoC.
>>
>> Reviewed-by: Jonathan Cameron
>> Signed-off-by: Shaokun Zhang
>> Signed-off-by: Anurup M
>> ---
>> Documentation/perf/hisi-pmu.txt | 52
>> +
>> 1 file changed, 52 insertions(+)
>> create mode 100644 Documentation/perf/hisi-pmu.txt
>>
>> diff --git a/Documentation/perf/hisi-pmu.txt
>> b/Documentation/perf/hisi-pmu.txt
>> new file mode 100644
>> index 000..f45a03d
>> --- /dev/null
>> +++ b/Documentation/perf/hisi-pmu.txt
>> @@ -0,0 +1,52 @@
>> +HiSilicon SoC uncore Performance Monitoring Unit (PMU)
>> +==
>> +The HiSilicon SoC chip comprehends various independent system device PMUs
>
> Nit: s/comprehends/comprises/ would be easier to read.
>
Ok.
>> +such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
>> +independent and have hardware logic to gather statistics and performance
>> +information.
>> +
>> +HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
>
> Nit: The Hisilicon SoC
>
Ok.
>> +(CCL) is made up of 4 cpu cores sharing one L3 cache; Each CPU die is
>
> Nit: s/Each/each/
>
Ok.
>> +called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
>> +two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
>> +
>> +HiSilicon SoC uncore PMU driver
>> +---
>> +Each device PMU has separate registers for event counting, control and
>> +interrupt, and the PMU driver shall register perf PMU drivers like L3C,
>> +HHA and DDRC etc. The available events and configuration options shall
>> +be described in the sysfs, see /sys/devices/hisi_*
>
> What exactly its exposed under /sys/devices/hisi_* ?
>
Apologies that i shall list /sys/devices/hisi_sccl{X}_/
and
will change it in next version.
>> or /sys/bus/
>> +event_source/devices/hisi_*.
>
> Please don't wrap paths; keep this on one line.
>
Ok.
>> +The "perf list" command shall list the available events from sysfs.
>> +
>> +Each L3C, HHA and DDRC in one SCCL are registered as an separate PMU with
>> perf.
>> +The PMU name will appear in event listing as hisi_module
>> _.
>> +where "index-id" is the index of module and "sccl-id" is the identifier of
>> +the SCCL.
>> +e.g. hisi_l3c0_1/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 and
>> SCCL
>> +ID #1.
>> +e.g. hisi_hha0_1/rx_operations is RX_OPERATIONS event of HHA index #0 and
>> SCCL
>> +ID #1.
>
> It would make more sense for this to be hierarichal, e.g. hisi_sccl{X}_l3c{Y}.
>
Surely, it is nicer.
Thanks.
Shaokun
> Other than the above nits, this documentation is very useful. Thanks for
> putting this together.
>
> Thanks,
> Mark.
> ___
> linuxarm mailing list
> linux...@huawei.com
> http://rnd-openeuler.huawei.com/mailman/listinfo/linuxarm
>
> .
>
Re: [PATCH v4 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
Hi,
On Tue, Jul 25, 2017 at 08:10:37PM +0800, Shaokun Zhang wrote:
> This patch adds documentation for the uncore PMUs on HiSilicon SoC.
>
> Reviewed-by: Jonathan Cameron
> Signed-off-by: Shaokun Zhang
> Signed-off-by: Anurup M
> ---
> Documentation/perf/hisi-pmu.txt | 52
> +
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/perf/hisi-pmu.txt
>
> diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt
> new file mode 100644
> index 000..f45a03d
> --- /dev/null
> +++ b/Documentation/perf/hisi-pmu.txt
> @@ -0,0 +1,52 @@
> +HiSilicon SoC uncore Performance Monitoring Unit (PMU)
> +==
> +The HiSilicon SoC chip comprehends various independent system device PMUs
Nit: s/comprehends/comprises/ would be easier to read.
> +such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
> +independent and have hardware logic to gather statistics and performance
> +information.
> +
> +HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster
Nit: The Hisilicon SoC
> +(CCL) is made up of 4 cpu cores sharing one L3 cache; Each CPU die is
Nit: s/Each/each/
> +called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has
> +two HHAs (0 - 1) and four DDRCs (0 - 3), respectively.
> +
> +HiSilicon SoC uncore PMU driver
> +---
> +Each device PMU has separate registers for event counting, control and
> +interrupt, and the PMU driver shall register perf PMU drivers like L3C,
> +HHA and DDRC etc. The available events and configuration options shall
> +be described in the sysfs, see /sys/devices/hisi_*
What exactly its exposed under /sys/devices/hisi_* ?
> or /sys/bus/
> +event_source/devices/hisi_*.
Please don't wrap paths; keep this on one line.
> +The "perf list" command shall list the available events from sysfs.
> +
> +Each L3C, HHA and DDRC in one SCCL are registered as an separate PMU with
> perf.
> +The PMU name will appear in event listing as hisi_module
> _.
> +where "index-id" is the index of module and "sccl-id" is the identifier of
> +the SCCL.
> +e.g. hisi_l3c0_1/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 and
> SCCL
> +ID #1.
> +e.g. hisi_hha0_1/rx_operations is RX_OPERATIONS event of HHA index #0 and
> SCCL
> +ID #1.
It would make more sense for this to be hierarichal, e.g. hisi_sccl{X}_l3c{Y}.
Other than the above nits, this documentation is very useful. Thanks for
putting this together.
Thanks,
Mark.
[PATCH v4 1/6] Documentation: perf: hisi: Documentation for HiSilicon SoC PMU driver
This patch adds documentation for the uncore PMUs on HiSilicon SoC. Reviewed-by: Jonathan Cameron Signed-off-by: Shaokun Zhang Signed-off-by: Anurup M --- Documentation/perf/hisi-pmu.txt | 52 + 1 file changed, 52 insertions(+) create mode 100644 Documentation/perf/hisi-pmu.txt diff --git a/Documentation/perf/hisi-pmu.txt b/Documentation/perf/hisi-pmu.txt new file mode 100644 index 000..f45a03d --- /dev/null +++ b/Documentation/perf/hisi-pmu.txt @@ -0,0 +1,52 @@ +HiSilicon SoC uncore Performance Monitoring Unit (PMU) +== +The HiSilicon SoC chip comprehends various independent system device PMUs +such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are +independent and have hardware logic to gather statistics and performance +information. + +HiSilicon SoC encapsulates multiple CPU and IO dies. Each CPU cluster +(CCL) is made up of 4 cpu cores sharing one L3 cache; Each CPU die is +called Super CPU cluster (SCCL) and is made up of 6 CCLs. Each SCCL has +two HHAs (0 - 1) and four DDRCs (0 - 3), respectively. + +HiSilicon SoC uncore PMU driver +--- +Each device PMU has separate registers for event counting, control and +interrupt, and the PMU driver shall register perf PMU drivers like L3C, +HHA and DDRC etc. The available events and configuration options shall +be described in the sysfs, see /sys/devices/hisi_* or /sys/bus/ +event_source/devices/hisi_*. +The "perf list" command shall list the available events from sysfs. + +Each L3C, HHA and DDRC in one SCCL are registered as an separate PMU with perf. +The PMU name will appear in event listing as hisi_module _. +where "index-id" is the index of module and "sccl-id" is the identifier of +the SCCL. +e.g. hisi_l3c0_1/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 and SCCL +ID #1. +e.g. hisi_hha0_1/rx_operations is RX_OPERATIONS event of HHA index #0 and SCCL +ID #1. + +The driver also provides a "cpumask" sysfs attribute, which shows the CPU core +ID used to count the uncore PMU event. + +Example usage of perf: +$# perf list +hisi_l3c0_3/rd_hit_cpipe/ [kernel PMU event] +-- +hisi_l3c0_3/wr_hit_cpipe/ [kernel PMU event] +-- +hisi_l3c0_1/rd_hit_cpipe/ [kernel PMU event] +-- +hisi_l3c0_1/wr_hit_cpipe/ [kernel PMU event] +-- + +$# perf stat -a -e hisi_l3c0_1/rd_hit_cpipe/ sleep 5 +$# perf stat -a -e hisi_l3c0_1/config=0x02/ sleep 5 + +The current driver does not support sampling. So "perf record" is unsupported. +Also attach to a task is unsupported as the events are all uncore. + +Note: Please contact the maintainer for a complete list of events supported for +the PMU devices in the SoC and its information if needed. -- 1.9.1
