Re: [PATCH v4 1/7] clk: mediatek: Add fixed clocks support for Mediatek SoC.

2015-07-27 Thread James Liao
Hi Daniel,

On Fri, 2015-07-24 at 19:33 +0800, Daniel Kurtz wrote:
> Hi James,
> 
> On Fri, Jul 24, 2015 at 11:01 AM, James Liao  
> wrote:
> >
> > +void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
> > +   struct clk_onecell_data *clk_data)
> 
> 
> void __init mtk_clk_register_fixed_clks(...

It will be added in next patch.


> > -extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
> > +void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
> 
> Technically, this hunk is unrelated and should probably be in its own patch.

It will be in a separated patch.


Best regards,

James


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Re: [PATCH v4 1/7] clk: mediatek: Add fixed clocks support for Mediatek SoC.

2015-07-27 Thread James Liao
Hi Daniel,

On Fri, 2015-07-24 at 19:33 +0800, Daniel Kurtz wrote:
 Hi James,
 
 On Fri, Jul 24, 2015 at 11:01 AM, James Liao jamesjj.l...@mediatek.com 
 wrote:
 
  +void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
  +   struct clk_onecell_data *clk_data)
 
 
 void __init mtk_clk_register_fixed_clks(...

It will be added in next patch.


  -extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
  +void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
 
 Technically, this hunk is unrelated and should probably be in its own patch.

It will be in a separated patch.


Best regards,

James


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Re: [PATCH v4 1/7] clk: mediatek: Add fixed clocks support for Mediatek SoC.

2015-07-24 Thread Daniel Kurtz
Hi James,

On Fri, Jul 24, 2015 at 11:01 AM, James Liao  wrote:
> This patch adds fixed clocks support by using CCF fixed-rate
> clock implementation.
>
> Signed-off-by: James Liao 
> ---
>  drivers/clk/mediatek/clk-mtk.c | 23 +++
>  drivers/clk/mediatek/clk-mtk.h | 19 ++-
>  2 files changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> index 18444ae..f8307c3 100644
> --- a/drivers/clk/mediatek/clk-mtk.c
> +++ b/drivers/clk/mediatek/clk-mtk.c
> @@ -49,6 +49,29 @@ err_out:
> return NULL;
>  }
>
> +void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
> +   struct clk_onecell_data *clk_data)


void __init mtk_clk_register_fixed_clks(...

> +{
> +   int i;
> +   struct clk *clk;
> +
> +   for (i = 0; i < num; i++) {
> +   const struct mtk_fixed_clk *rc = [i];
> +
> +   clk = clk_register_fixed_rate(NULL, rc->name, rc->parent,
> +   rc->parent ? 0 : CLK_IS_ROOT, rc->rate);
> +
> +   if (IS_ERR(clk)) {
> +   pr_err("Failed to register clk %s: %ld\n",
> +   rc->name, PTR_ERR(clk));
> +   continue;
> +   }
> +
> +   if (clk_data)
> +   clk_data->clks[rc->id] = clk;
> +   }
> +}
> +
>  void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
> struct clk_onecell_data *clk_data)
>  {
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index 9dda9d8..f083dfc 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -25,6 +25,23 @@
>
>  #define MHZ (1000 * 1000)
>
> +struct mtk_fixed_clk {
> +   int id;
> +   const char *name;
> +   const char *parent;
> +   unsigned long rate;
> +};
> +
> +#define FIXED_CLK(_id, _name, _parent, _rate) {\
> +   .id = _id,  \
> +   .name = _name,  \
> +   .parent = _parent,  \
> +   .rate = _rate,  \
> +   }
> +
> +void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
> +   int num, struct clk_onecell_data *clk_data);
> +
>  struct mtk_fixed_factor {
> int id;
> const char *name;
> @@ -41,7 +58,7 @@ struct mtk_fixed_factor {
> .div = _div,\
> }
>
> -extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
> +void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,

Technically, this hunk is unrelated and should probably be in its own patch.

Other than these two nits, this one is:

Reviewed-by: Daniel Kurtz 

> int num, struct clk_onecell_data *clk_data);
>
>  struct mtk_composite {
> --
> 1.8.1.1.dirty
>
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Re: [PATCH v4 1/7] clk: mediatek: Add fixed clocks support for Mediatek SoC.

2015-07-24 Thread Daniel Kurtz
Hi James,

On Fri, Jul 24, 2015 at 11:01 AM, James Liao jamesjj.l...@mediatek.com wrote:
 This patch adds fixed clocks support by using CCF fixed-rate
 clock implementation.

 Signed-off-by: James Liao jamesjj.l...@mediatek.com
 ---
  drivers/clk/mediatek/clk-mtk.c | 23 +++
  drivers/clk/mediatek/clk-mtk.h | 19 ++-
  2 files changed, 41 insertions(+), 1 deletion(-)

 diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
 index 18444ae..f8307c3 100644
 --- a/drivers/clk/mediatek/clk-mtk.c
 +++ b/drivers/clk/mediatek/clk-mtk.c
 @@ -49,6 +49,29 @@ err_out:
 return NULL;
  }

 +void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
 +   struct clk_onecell_data *clk_data)


void __init mtk_clk_register_fixed_clks(...

 +{
 +   int i;
 +   struct clk *clk;
 +
 +   for (i = 0; i  num; i++) {
 +   const struct mtk_fixed_clk *rc = clks[i];
 +
 +   clk = clk_register_fixed_rate(NULL, rc-name, rc-parent,
 +   rc-parent ? 0 : CLK_IS_ROOT, rc-rate);
 +
 +   if (IS_ERR(clk)) {
 +   pr_err(Failed to register clk %s: %ld\n,
 +   rc-name, PTR_ERR(clk));
 +   continue;
 +   }
 +
 +   if (clk_data)
 +   clk_data-clks[rc-id] = clk;
 +   }
 +}
 +
  void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
 struct clk_onecell_data *clk_data)
  {
 diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
 index 9dda9d8..f083dfc 100644
 --- a/drivers/clk/mediatek/clk-mtk.h
 +++ b/drivers/clk/mediatek/clk-mtk.h
 @@ -25,6 +25,23 @@

  #define MHZ (1000 * 1000)

 +struct mtk_fixed_clk {
 +   int id;
 +   const char *name;
 +   const char *parent;
 +   unsigned long rate;
 +};
 +
 +#define FIXED_CLK(_id, _name, _parent, _rate) {\
 +   .id = _id,  \
 +   .name = _name,  \
 +   .parent = _parent,  \
 +   .rate = _rate,  \
 +   }
 +
 +void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
 +   int num, struct clk_onecell_data *clk_data);
 +
  struct mtk_fixed_factor {
 int id;
 const char *name;
 @@ -41,7 +58,7 @@ struct mtk_fixed_factor {
 .div = _div,\
 }

 -extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
 +void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,

Technically, this hunk is unrelated and should probably be in its own patch.

Other than these two nits, this one is:

Reviewed-by: Daniel Kurtz djku...@chromium.org

 int num, struct clk_onecell_data *clk_data);

  struct mtk_composite {
 --
 1.8.1.1.dirty

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[PATCH v4 1/7] clk: mediatek: Add fixed clocks support for Mediatek SoC.

2015-07-23 Thread James Liao
This patch adds fixed clocks support by using CCF fixed-rate
clock implementation.

Signed-off-by: James Liao 
---
 drivers/clk/mediatek/clk-mtk.c | 23 +++
 drivers/clk/mediatek/clk-mtk.h | 19 ++-
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 18444ae..f8307c3 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -49,6 +49,29 @@ err_out:
return NULL;
 }
 
+void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
+   struct clk_onecell_data *clk_data)
+{
+   int i;
+   struct clk *clk;
+
+   for (i = 0; i < num; i++) {
+   const struct mtk_fixed_clk *rc = [i];
+
+   clk = clk_register_fixed_rate(NULL, rc->name, rc->parent,
+   rc->parent ? 0 : CLK_IS_ROOT, rc->rate);
+
+   if (IS_ERR(clk)) {
+   pr_err("Failed to register clk %s: %ld\n",
+   rc->name, PTR_ERR(clk));
+   continue;
+   }
+
+   if (clk_data)
+   clk_data->clks[rc->id] = clk;
+   }
+}
+
 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
struct clk_onecell_data *clk_data)
 {
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 9dda9d8..f083dfc 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -25,6 +25,23 @@
 
 #define MHZ (1000 * 1000)
 
+struct mtk_fixed_clk {
+   int id;
+   const char *name;
+   const char *parent;
+   unsigned long rate;
+};
+
+#define FIXED_CLK(_id, _name, _parent, _rate) {\
+   .id = _id,  \
+   .name = _name,  \
+   .parent = _parent,  \
+   .rate = _rate,  \
+   }
+
+void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
+   int num, struct clk_onecell_data *clk_data);
+
 struct mtk_fixed_factor {
int id;
const char *name;
@@ -41,7 +58,7 @@ struct mtk_fixed_factor {
.div = _div,\
}
 
-extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
+void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
int num, struct clk_onecell_data *clk_data);
 
 struct mtk_composite {
-- 
1.8.1.1.dirty

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[PATCH v4 1/7] clk: mediatek: Add fixed clocks support for Mediatek SoC.

2015-07-23 Thread James Liao
This patch adds fixed clocks support by using CCF fixed-rate
clock implementation.

Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
 drivers/clk/mediatek/clk-mtk.c | 23 +++
 drivers/clk/mediatek/clk-mtk.h | 19 ++-
 2 files changed, 41 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 18444ae..f8307c3 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -49,6 +49,29 @@ err_out:
return NULL;
 }
 
+void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks, int num,
+   struct clk_onecell_data *clk_data)
+{
+   int i;
+   struct clk *clk;
+
+   for (i = 0; i  num; i++) {
+   const struct mtk_fixed_clk *rc = clks[i];
+
+   clk = clk_register_fixed_rate(NULL, rc-name, rc-parent,
+   rc-parent ? 0 : CLK_IS_ROOT, rc-rate);
+
+   if (IS_ERR(clk)) {
+   pr_err(Failed to register clk %s: %ld\n,
+   rc-name, PTR_ERR(clk));
+   continue;
+   }
+
+   if (clk_data)
+   clk_data-clks[rc-id] = clk;
+   }
+}
+
 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num,
struct clk_onecell_data *clk_data)
 {
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index 9dda9d8..f083dfc 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -25,6 +25,23 @@
 
 #define MHZ (1000 * 1000)
 
+struct mtk_fixed_clk {
+   int id;
+   const char *name;
+   const char *parent;
+   unsigned long rate;
+};
+
+#define FIXED_CLK(_id, _name, _parent, _rate) {\
+   .id = _id,  \
+   .name = _name,  \
+   .parent = _parent,  \
+   .rate = _rate,  \
+   }
+
+void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
+   int num, struct clk_onecell_data *clk_data);
+
 struct mtk_fixed_factor {
int id;
const char *name;
@@ -41,7 +58,7 @@ struct mtk_fixed_factor {
.div = _div,\
}
 
-extern void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
+void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
int num, struct clk_onecell_data *clk_data);
 
 struct mtk_composite {
-- 
1.8.1.1.dirty

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