subject:"\[PATCH v4 16\/16\] soc\: mediatek\: pm\-domains\: Add support for mt8192"

Re: [PATCH v4 16/16] soc: mediatek: pm-domains: Add support for mt8192

2020-11-19 Thread Weiyi Lu

On Fri, 2020-10-30 at 12:36 +0100, Enric Balletbo i Serra wrote:
> From: Weiyi Lu 
> 
> Add the needed board data to support mt8192 SoC.
> 
> Signed-off-by: Weiyi Lu 
> Signed-off-by: Enric Balletbo i Serra 
> ---
> 

Hi Enric,

I've verified with my dts v3[1] on MT8192 EVB, so

Tested-by: Weiyi Lu 

[1]
https://patchwork.kernel.org/project/linux-mediatek/list/?series=387453

> Changes in v4:
> - Adapt scpsys_soc_data struct to the changes done in previous patches.
> 
> Changes in v3: None
> Changes in v2: None
> 
>  drivers/soc/mediatek/mt8192-pm-domains.h | 292 +++
>  drivers/soc/mediatek/mtk-pm-domains.c|   5 +
>  include/linux/soc/mediatek/infracfg.h|  56 +
>  3 files changed, 353 insertions(+)
>  create mode 100644 drivers/soc/mediatek/mt8192-pm-domains.h
> 
> diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h 
> b/drivers/soc/mediatek/mt8192-pm-domains.h
> new file mode 100644
> index ..0fdf6dc6231f
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8192-pm-domains.h
> @@ -0,0 +1,292 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
> +#define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
> +
> +#include "mtk-pm-domains.h"
> +#include 
> +
> +/*
> + * MT8192 power domain support
> + */
> +
> +static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> + [MT8192_POWER_DOMAIN_AUDIO] = {
> + .sta_mask = BIT(21),
> + .ctl_offs = 0x0354,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
> + MT8192_TOP_AXI_PROT_EN_2_SET,
> + MT8192_TOP_AXI_PROT_EN_2_CLR,
> + MT8192_TOP_AXI_PROT_EN_2_STA1),
> + },
> + },
> + [MT8192_POWER_DOMAIN_CONN] = {
> + .sta_mask = PWR_STATUS_CONN,
> + .ctl_offs = 0x0304,
> + .sram_pdn_bits = 0,
> + .sram_pdn_ack_bits = 0,
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN,
> + MT8192_TOP_AXI_PROT_EN_SET,
> + MT8192_TOP_AXI_PROT_EN_CLR,
> + MT8192_TOP_AXI_PROT_EN_STA1),
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
> + MT8192_TOP_AXI_PROT_EN_SET,
> + MT8192_TOP_AXI_PROT_EN_CLR,
> + MT8192_TOP_AXI_PROT_EN_STA1),
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
> + MT8192_TOP_AXI_PROT_EN_1_SET,
> + MT8192_TOP_AXI_PROT_EN_1_CLR,
> + MT8192_TOP_AXI_PROT_EN_1_STA1),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8192_POWER_DOMAIN_MFG0] = {
> + .sta_mask = BIT(2),
> + .ctl_offs = 0x0308,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT8192_POWER_DOMAIN_MFG1] = {
> + .sta_mask = BIT(3),
> + .ctl_offs = 0x030c,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
> + MT8192_TOP_AXI_PROT_EN_1_SET,
> + MT8192_TOP_AXI_PROT_EN_1_CLR,
> + MT8192_TOP_AXI_PROT_EN_1_STA1),
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
> + MT8192_TOP_AXI_PROT_EN_2_SET,
> + MT8192_TOP_AXI_PROT_EN_2_CLR,
> + MT8192_TOP_AXI_PROT_EN_2_STA1),
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
> + MT8192_TOP_AXI_PROT_EN_SET,
> + MT8192_TOP_AXI_PROT_EN_CLR,
> + MT8192_TOP_AXI_PROT_EN_STA1),
> + BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
> + MT8192_TOP_AXI_PROT_EN_2_SET,
> + MT8192_TOP_AXI_PROT_EN_2_CLR,
> + MT8192_TOP_AXI_PROT_EN_2_STA1),
> + },
> + },
> + [MT8192_POWER_DOMAIN_MFG2] = {
> + .sta_mask = BIT(4),
> + .ctl_offs = 0x0310,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits = GENMASK(12, 12),
> + },
> + [MT8192_POWER_DOMAIN_MFG3] = {
> + .sta_mask = BIT(5),
> + .ctl_offs = 0x0314,
> + .sram_pdn_bits = GENMASK(8, 8),
> + .sram_pdn_ack_bits

[PATCH v4 16/16] soc: mediatek: pm-domains: Add support for mt8192

2020-10-30 Thread Enric Balletbo i Serra

From: Weiyi Lu 

Add the needed board data to support mt8192 SoC.

Signed-off-by: Weiyi Lu 
Signed-off-by: Enric Balletbo i Serra 
---

Changes in v4:
- Adapt scpsys_soc_data struct to the changes done in previous patches.

Changes in v3: None
Changes in v2: None

 drivers/soc/mediatek/mt8192-pm-domains.h | 292 +++
 drivers/soc/mediatek/mtk-pm-domains.c|   5 +
 include/linux/soc/mediatek/infracfg.h|  56 +
 3 files changed, 353 insertions(+)
 create mode 100644 drivers/soc/mediatek/mt8192-pm-domains.h

diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h 
b/drivers/soc/mediatek/mt8192-pm-domains.h
new file mode 100644
index ..0fdf6dc6231f
--- /dev/null
+++ b/drivers/soc/mediatek/mt8192-pm-domains.h
@@ -0,0 +1,292 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include 
+
+/*
+ * MT8192 power domain support
+ */
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
+   [MT8192_POWER_DOMAIN_AUDIO] = {
+   .sta_mask = BIT(21),
+   .ctl_offs = 0x0354,
+   .sram_pdn_bits = GENMASK(8, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .bp_infracfg = {
+   BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
+   MT8192_TOP_AXI_PROT_EN_2_SET,
+   MT8192_TOP_AXI_PROT_EN_2_CLR,
+   MT8192_TOP_AXI_PROT_EN_2_STA1),
+   },
+   },
+   [MT8192_POWER_DOMAIN_CONN] = {
+   .sta_mask = PWR_STATUS_CONN,
+   .ctl_offs = 0x0304,
+   .sram_pdn_bits = 0,
+   .sram_pdn_ack_bits = 0,
+   .bp_infracfg = {
+   BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN,
+   MT8192_TOP_AXI_PROT_EN_SET,
+   MT8192_TOP_AXI_PROT_EN_CLR,
+   MT8192_TOP_AXI_PROT_EN_STA1),
+   BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
+   MT8192_TOP_AXI_PROT_EN_SET,
+   MT8192_TOP_AXI_PROT_EN_CLR,
+   MT8192_TOP_AXI_PROT_EN_STA1),
+   BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
+   MT8192_TOP_AXI_PROT_EN_1_SET,
+   MT8192_TOP_AXI_PROT_EN_1_CLR,
+   MT8192_TOP_AXI_PROT_EN_1_STA1),
+   },
+   .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+   },
+   [MT8192_POWER_DOMAIN_MFG0] = {
+   .sta_mask = BIT(2),
+   .ctl_offs = 0x0308,
+   .sram_pdn_bits = GENMASK(8, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   },
+   [MT8192_POWER_DOMAIN_MFG1] = {
+   .sta_mask = BIT(3),
+   .ctl_offs = 0x030c,
+   .sram_pdn_bits = GENMASK(8, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   .bp_infracfg = {
+   BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
+   MT8192_TOP_AXI_PROT_EN_1_SET,
+   MT8192_TOP_AXI_PROT_EN_1_CLR,
+   MT8192_TOP_AXI_PROT_EN_1_STA1),
+   BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
+   MT8192_TOP_AXI_PROT_EN_2_SET,
+   MT8192_TOP_AXI_PROT_EN_2_CLR,
+   MT8192_TOP_AXI_PROT_EN_2_STA1),
+   BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
+   MT8192_TOP_AXI_PROT_EN_SET,
+   MT8192_TOP_AXI_PROT_EN_CLR,
+   MT8192_TOP_AXI_PROT_EN_STA1),
+   BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
+   MT8192_TOP_AXI_PROT_EN_2_SET,
+   MT8192_TOP_AXI_PROT_EN_2_CLR,
+   MT8192_TOP_AXI_PROT_EN_2_STA1),
+   },
+   },
+   [MT8192_POWER_DOMAIN_MFG2] = {
+   .sta_mask = BIT(4),
+   .ctl_offs = 0x0310,
+   .sram_pdn_bits = GENMASK(8, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   },
+   [MT8192_POWER_DOMAIN_MFG3] = {
+   .sta_mask = BIT(5),
+   .ctl_offs = 0x0314,
+   .sram_pdn_bits = GENMASK(8, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   },
+   [MT8192_POWER_DOMAIN_MFG4] = {
+   .sta_mask = BIT(6),
+   .ctl_offs = 0x0318,
+   .sram_pdn_bits = GENMASK(8, 8),
+   .sram_pdn_ack_bits = GENMASK(12, 12),
+   },
+   [MT8192_POWER_DOMAIN_MFG5] = {
+

Re: [PATCH v4 16/16] soc: mediatek: pm-domains: Add support for mt8192

[PATCH v4 16/16] soc: mediatek: pm-domains: Add support for mt8192

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