Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

[James Hogan]

On Thu, Apr 12, 2018 at 10:33:42PM -0400, Sinan Kaya wrote:
> On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> > +   /* prevent prefetching of coherent DMA dma prematurely */   \
> 
> I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
> posting another version until I hear back from you for wmb().

No problem, I've applied both for 4.17 and tweaked the comment.

Thanks
James


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Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

[James Hogan]

On Thu, Apr 12, 2018 at 10:33:42PM -0400, Sinan Kaya wrote:
> On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> > +   /* prevent prefetching of coherent DMA dma prematurely */   \
> 
> I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
> posting another version until I hear back from you for wmb().

No problem, I've applied both for 4.17 and tweaked the comment.

Thanks
James


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Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

[Sinan Kaya]

On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> + /* prevent prefetching of coherent DMA dma prematurely */   \

I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
posting another version until I hear back from you for wmb().

-- 
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux 
Foundation Collaborative Project.

Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

[Sinan Kaya]

On 4/12/2018 10:30 PM, Sinan Kaya wrote:
> + /* prevent prefetching of coherent DMA dma prematurely */   \

I tried to write DMA data but my keyboard is not cooperating. I'll hold onto
posting another version until I hear back from you for wmb().

-- 
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm 
Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux 
Foundation Collaborative Project.

[PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

[Sinan Kaya]

While a barrier is present in writeX() function before the register write,
a similar barrier is missing in the readX() function after the register
read. This could allow memory accesses following readX() to observe
stale data.

Signed-off-by: Sinan Kaya 
Reported-by: Arnd Bergmann 
---
 arch/mips/include/asm/io.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index fd00ddaf..d96af41 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const volatile void 
__iomem *mem)\
BUG();  \
}   \
\
+   /* prevent prefetching of coherent DMA dma prematurely */   \
+   rmb();  \
return pfx##ioswab##bwlq(__mem, __val); \
 }
 
-- 
2.7.4

[PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

[Sinan Kaya]

While a barrier is present in writeX() function before the register write,
a similar barrier is missing in the readX() function after the register
read. This could allow memory accesses following readX() to observe
stale data.

Signed-off-by: Sinan Kaya 
Reported-by: Arnd Bergmann 
---
 arch/mips/include/asm/io.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index fd00ddaf..d96af41 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,8 @@ static inline type pfx##read##bwlq(const volatile void 
__iomem *mem)\
BUG();  \
}   \
\
+   /* prevent prefetching of coherent DMA dma prematurely */   \
+   rmb();  \
return pfx##ioswab##bwlq(__mem, __val); \
 }
 
-- 
2.7.4