Re: [RESEND, PATCH v4 2/2] dt-bindings: cpufreq: Document allwinner,sun50i-h6-operating-points
On Wed, 12 Jun 2019 12:28:16 -0400, Yangtao Li wrote: > Allwinner Process Voltage Scaling Tables defines the voltage and > frequency value based on the speedbin blown in the efuse combination. > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > provide the OPP framework with required information. > This is used to determine the voltage and frequency value for each > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > The "allwinner,sun50i-h6-operating-points" DT extends the > "operating-points-v2" > with following parameters: > - nvmem-cells (NVMEM area containig the speedbin information) > - opp-microvolt-: voltage in micro Volts. > At runtime, the platform can pick a and matching > opp-microvolt- property. > HW: : > sun50i-h6 speed0 speed1 speed2 > > Signed-off-by: Yangtao Li > Acked-by: Maxime Ripard > --- > .../bindings/opp/sun50i-nvmem-cpufreq.txt | 167 ++ > 1 file changed, 167 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt > Reviewed-by: Rob Herring
[RESEND, PATCH v4 2/2] dt-bindings: cpufreq: Document allwinner,sun50i-h6-operating-points
Allwinner Process Voltage Scaling Tables defines the voltage and
frequency value based on the speedbin blown in the efuse combination.
The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to
provide the OPP framework with required information.
This is used to determine the voltage and frequency value for each
OPP of operating-points-v2 table when it is parsed by the OPP framework.
The "allwinner,sun50i-h6-operating-points" DT extends the
"operating-points-v2"
with following parameters:
- nvmem-cells (NVMEM area containig the speedbin information)
- opp-microvolt-: voltage in micro Volts.
At runtime, the platform can pick a and matching
opp-microvolt- property.
HW: :
sun50i-h6 speed0 speed1 speed2
Signed-off-by: Yangtao Li
Acked-by: Maxime Ripard
---
.../bindings/opp/sun50i-nvmem-cpufreq.txt | 167 ++
1 file changed, 167 insertions(+)
create mode 100644
Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt
diff --git a/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt
b/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt
new file mode 100644
index ..7deae57a587b
--- /dev/null
+++ b/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt
@@ -0,0 +1,167 @@
+Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
+===
+
+For some SoCs, the CPU frequency subset and voltage value of each OPP
+varies based on the silicon variant in use. Allwinner Process Voltage
+Scaling Tables defines the voltage and frequency value based on the
+speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver
+reads the efuse value from the SoC to provide the OPP framework with
+required information.
+
+Required properties:
+
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+ - 'allwinner,sun50i-h6-operating-points'.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+ efuse registers that has information about the speedbin
+ that is used to select the right frequency/voltage value
+ pair. Please refer the for nvmem-cells bindings
+ Documentation/devicetree/bindings/nvmem/nvmem.txt and
+ also examples below.
+
+In every OPP node:
+- opp-microvolt-: Voltage in micro Volts.
+ At runtime, the platform can pick a and
+ matching opp-microvolt- property.
+ [See: opp.txt]
+ HW: :
+ sun50i-h6 speed0 speed1 speed2
+
+Example 1:
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+};
+
+cpu_opp_table: opp_table {
+compatible = "allwinner,sun50i-h6-operating-points";
+nvmem-cells = <_efuse>;
+opp-shared;
+
+opp@48000 {
+clock-latency-ns
Re: [PATCH v4 2/2] dt-bindings: cpufreq: Document allwinner,sun50i-h6-operating-points
On Wed, Apr 17, 2019 at 4:30 PM Maxime Ripard wrote: > > On Tue, Apr 16, 2019 at 11:52:09AM -0400, Yangtao Li wrote: > > Allwinner Process Voltage Scaling Tables defines the voltage and > > frequency value based on the speedbin blown in the efuse combination. > > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > > provide the OPP framework with required information. > > This is used to determine the voltage and frequency value for each > > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > > > The "allwinner,sun50i-h6-operating-points" DT extends the > > "operating-points-v2" > > with following parameters: > > - nvmem-cells (NVMEM area containig the speedbin information) > > - opp-microvolt-: voltage in micro Volts. > > At runtime, the platform can pick a and matching > > opp-microvolt- property. > > HW: : > > sun50iw-h6 speed0 speed1 speed2 > > > > Signed-off-by: Yangtao Li > > --- > > .../bindings/opp/sun50i-nvmem-cpufreq.txt | 167 ++ > > 1 file changed, 167 insertions(+) > > create mode 100644 > > Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt > > > > diff --git a/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt > > b/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt > > new file mode 100644 > > index ..3cb39c6caec3 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt > > @@ -0,0 +1,167 @@ > > +Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings > > +=== > > + > > +For some SoCs, the CPU frequency subset and voltage value of each OPP > > +varies based on the silicon variant in use. Allwinner Process Voltage > > +Scaling Tables defines the voltage and frequency value based on the > > +speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver > > +reads the efuse value from the SoC to provide the OPP framework with > > +required information. > > + > > +Required properties: > > + > > +In 'cpus' nodes: > > +- operating-points-v2: Phandle to the operating-points-v2 table to use. > > + > > +In 'operating-points-v2' table: > > +- compatible: Should be > > + - 'allwinner,sun50i-h6-operating-points'. > > +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the > > + efuse registers that has information about the speedbin > > + that is used to select the right frequency/voltage value > > + pair. Please refer the for nvmem-cells bindings > > + Documentation/devicetree/bindings/nvmem/nvmem.txt and > > + also examples below. > > + > > +In every OPP node: > > +- opp-microvolt-: Voltage in micro Volts. > > + At runtime, the platform can pick a and > > + matching opp-microvolt- property. > > + [See: opp.txt] > > + HW: : > > + sun50iw-h6 speed0 speed1 speed2 > > There's a typo here (and in your commit log), it should be sun50i-h6 > instead of sun50iw-h6 > > Once fixed: > Acked-by: Maxime Ripard Another has been sent. Regards, Yangtao
Re: [PATCH v4 2/2] dt-bindings: cpufreq: Document allwinner,sun50i-h6-operating-points
On Tue, Apr 16, 2019 at 11:52:09AM -0400, Yangtao Li wrote: > Allwinner Process Voltage Scaling Tables defines the voltage and > frequency value based on the speedbin blown in the efuse combination. > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > provide the OPP framework with required information. > This is used to determine the voltage and frequency value for each > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > The "allwinner,sun50i-h6-operating-points" DT extends the > "operating-points-v2" > with following parameters: > - nvmem-cells (NVMEM area containig the speedbin information) > - opp-microvolt-: voltage in micro Volts. > At runtime, the platform can pick a and matching > opp-microvolt- property. > HW: : > sun50iw-h6 speed0 speed1 speed2 > > Signed-off-by: Yangtao Li > --- > .../bindings/opp/sun50i-nvmem-cpufreq.txt | 167 ++ > 1 file changed, 167 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt > > diff --git a/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt > b/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt > new file mode 100644 > index ..3cb39c6caec3 > --- /dev/null > +++ b/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt > @@ -0,0 +1,167 @@ > +Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings > +=== > + > +For some SoCs, the CPU frequency subset and voltage value of each OPP > +varies based on the silicon variant in use. Allwinner Process Voltage > +Scaling Tables defines the voltage and frequency value based on the > +speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver > +reads the efuse value from the SoC to provide the OPP framework with > +required information. > + > +Required properties: > + > +In 'cpus' nodes: > +- operating-points-v2: Phandle to the operating-points-v2 table to use. > + > +In 'operating-points-v2' table: > +- compatible: Should be > + - 'allwinner,sun50i-h6-operating-points'. > +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the > + efuse registers that has information about the speedbin > + that is used to select the right frequency/voltage value > + pair. Please refer the for nvmem-cells bindings > + Documentation/devicetree/bindings/nvmem/nvmem.txt and > + also examples below. > + > +In every OPP node: > +- opp-microvolt-: Voltage in micro Volts. > + At runtime, the platform can pick a and > + matching opp-microvolt- property. > + [See: opp.txt] > + HW: : > + sun50iw-h6 speed0 speed1 speed2 There's a typo here (and in your commit log), it should be sun50i-h6 instead of sun50iw-h6 Once fixed: Acked-by: Maxime Ripard Thanks! Maxime -- Maxime Ripard, Bootlin Embedded Linux and Kernel engineering https://bootlin.com signature.asc Description: PGP signature
Re: [PATCH v4 2/2] dt-bindings: cpufreq: Document allwinner,sun50i-h6-operating-points
On 16-04-19, 11:52, Yangtao Li wrote: > Allwinner Process Voltage Scaling Tables defines the voltage and > frequency value based on the speedbin blown in the efuse combination. > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > provide the OPP framework with required information. > This is used to determine the voltage and frequency value for each > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > The "allwinner,sun50i-h6-operating-points" DT extends the > "operating-points-v2" > with following parameters: > - nvmem-cells (NVMEM area containig the speedbin information) > - opp-microvolt-: voltage in micro Volts. > At runtime, the platform can pick a and matching > opp-microvolt- property. > HW: : > sun50iw-h6 speed0 speed1 speed2 > > Signed-off-by: Yangtao Li > --- > .../bindings/opp/sun50i-nvmem-cpufreq.txt | 167 ++ > 1 file changed, 167 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt I would need an Ack from Rob before applying this. -- viresh
[PATCH v4 2/2] dt-bindings: cpufreq: Document allwinner,sun50i-h6-operating-points
Allwinner Process Voltage Scaling Tables defines the voltage and
frequency value based on the speedbin blown in the efuse combination.
The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to
provide the OPP framework with required information.
This is used to determine the voltage and frequency value for each
OPP of operating-points-v2 table when it is parsed by the OPP framework.
The "allwinner,sun50i-h6-operating-points" DT extends the
"operating-points-v2"
with following parameters:
- nvmem-cells (NVMEM area containig the speedbin information)
- opp-microvolt-: voltage in micro Volts.
At runtime, the platform can pick a and matching
opp-microvolt- property.
HW: :
sun50iw-h6 speed0 speed1 speed2
Signed-off-by: Yangtao Li
---
.../bindings/opp/sun50i-nvmem-cpufreq.txt | 167 ++
1 file changed, 167 insertions(+)
create mode 100644
Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt
diff --git a/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt
b/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt
new file mode 100644
index ..3cb39c6caec3
--- /dev/null
+++ b/Documentation/devicetree/bindings/opp/sun50i-nvmem-cpufreq.txt
@@ -0,0 +1,167 @@
+Allwinner Technologies, Inc. NVMEM CPUFreq and OPP bindings
+===
+
+For some SoCs, the CPU frequency subset and voltage value of each OPP
+varies based on the silicon variant in use. Allwinner Process Voltage
+Scaling Tables defines the voltage and frequency value based on the
+speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver
+reads the efuse value from the SoC to provide the OPP framework with
+required information.
+
+Required properties:
+
+In 'cpus' nodes:
+- operating-points-v2: Phandle to the operating-points-v2 table to use.
+
+In 'operating-points-v2' table:
+- compatible: Should be
+ - 'allwinner,sun50i-h6-operating-points'.
+- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
+ efuse registers that has information about the speedbin
+ that is used to select the right frequency/voltage value
+ pair. Please refer the for nvmem-cells bindings
+ Documentation/devicetree/bindings/nvmem/nvmem.txt and
+ also examples below.
+
+In every OPP node:
+- opp-microvolt-: Voltage in micro Volts.
+ At runtime, the platform can pick a and
+ matching opp-microvolt- property.
+ [See: opp.txt]
+ HW: :
+ sun50iw-h6 speed0 speed1 speed2
+
+Example 1:
+-
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <2>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <3>;
+ enable-method = "psci";
+ clocks = < CLK_CPUX>;
+ clock-latency-ns = <244144>; /* 8 32k periods */
+ operating-points-v2 = <_opp_table>;
+ #cooling-cells = <2>;
+ };
+};
+
+cpu_opp_table: opp_table {
+compatible = "allwinner,sun50i-h6-operating-points";
+nvmem-cells = <_efuse>;
+opp-shared;
+
+opp@48000 {
+clock-latency-ns = <244144>; /* 8 32k
