Re: [PATCH v4 2/9] dt-bindings: spi: Add Tegra Quad SPI device tree binding

2020-12-21 Thread Rob Herring
On Thu, 17 Dec 2020 12:28:40 -0800, Sowjanya Komatineni wrote:
> This patch adds YAML based device tree binding document for Tegra
> Quad SPI driver.
> 
> Signed-off-by: Sowjanya Komatineni 
> ---
>  .../bindings/spi/nvidia,tegra210-quad.yaml | 117 
> +
>  1 file changed, 117 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
> 

Reviewed-by: Rob Herring 


[PATCH v4 2/9] dt-bindings: spi: Add Tegra Quad SPI device tree binding

2020-12-17 Thread Sowjanya Komatineni
This patch adds YAML based device tree binding document for Tegra
Quad SPI driver.

Signed-off-by: Sowjanya Komatineni 
---
 .../bindings/spi/nvidia,tegra210-quad.yaml | 117 +
 1 file changed, 117 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml

diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml 
b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
new file mode 100644
index 000..35a8045
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/nvidia,tegra210-quad.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tegra Quad SPI Controller
+
+maintainers:
+  - Thierry Reding 
+  - Jonathan Hunter 
+
+allOf:
+  - $ref: "spi-controller.yaml#"
+
+properties:
+  compatible:
+enum:
+  - nvidia,tegra210-qspi
+  - nvidia,tegra186-qspi
+  - nvidia,tegra194-qspi
+
+  reg:
+maxItems: 1
+
+  interrupts:
+maxItems: 1
+
+  clock-names:
+items:
+  - const: qspi
+  - const: qspi_out
+
+  clocks:
+maxItems: 2
+
+  resets:
+maxItems: 1
+
+  dmas:
+maxItems: 2
+
+  dma-names:
+items:
+  - const: rx
+  - const: tx
+
+patternProperties:
+  "@[0-9a-f]+":
+type: object
+
+properties:
+  spi-rx-bus-width:
+enum: [1, 2, 4]
+
+  spi-tx-bus-width:
+enum: [1, 2, 4]
+
+  nvidia,tx-clk-tap-delay:
+description:
+  Delays the clock going out to device with this tap value.
+  Tap value varies based on platform design trace lengths from Tegra
+  QSPI to corresponding slave device.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0
+maximum: 31
+
+  nvidia,rx-clk-tap-delay:
+description:
+  Delays the clock coming in from the device with this tap value.
+  Tap value varies based on platform design trace lengths from Tegra
+  QSPI to corresponding slave device.
+$ref: /schemas/types.yaml#/definitions/uint32
+minimum: 0
+maximum: 255
+
+required:
+  - reg
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clock-names
+  - clocks
+  - resets
+
+unevaluatedProperties: false
+
+examples:
+  - |
+#include 
+#include 
+#include 
+spi@7041 {
+compatible = "nvidia,tegra210-qspi";
+reg = <0x7041 0x1000>;
+interrupts = ;
+#address-cells = <1>;
+#size-cells = <0>;
+clocks = <_car TEGRA210_CLK_QSPI>,
+ <_car TEGRA210_CLK_QSPI_PM>;
+clock-names = "qspi", "qspi_out";
+resets = <_car 211>;
+dmas = < 5>, < 5>;
+dma-names = "rx", "tx";
+
+flash@0 {
+compatible = "spi-nor";
+reg = <0>;
+spi-max-frequency = <10400>;
+spi-tx-bus-width = <2>;
+spi-rx-bus-width = <2>;
+nvidia,tx-clk-tap-delay = <0>;
+nvidia,rx-clk-tap-delay = <0>;
+};
+};
-- 
2.7.4