Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
On 02/22/2018 04:53 AM, Doug Anderson wrote: > Hi, > > On Mon, Feb 19, 2018 at 8:36 AM, Marc Zyngier wrote: >>> + interrupts = ; >> >> Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC >> binding. Set it to the actual trigger value. >> > >>> + interrupts = ; >> >> Same here. > > Thanks for the review Marc! > > > Andy: If I'm reading everything correctly you're the one who would > collect these patches and apply them. Is that right? Do they look OK > to you in general? Would you prefer that Rajendra send out a v5 with > the fixes pointed out by Marc, or would you prefer to fix them up > yourself when applying? Is now a good time or would you prefer to > wait? I just fixed up to remove all instances of IRQ_TYPE_NONE and sent a v5 out. > > Thanks! :) > > -Doug > > ___ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
On 02/19/2018 10:06 PM, Marc Zyngier wrote:
> On Fri, 16 Feb 2018 11:35:02 +0530
> Rajendra Nayak wrote:
>
>> Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
>>
>> Signed-off-by: Rajendra Nayak
>> Reviewed-by: Doug Anderson
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 1 +
>> arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++
>> arch/arm64/boot/dts/qcom/sdm845.dtsi| 277
>>
>> 3 files changed, 293 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi
[...]
>> +
>> +soc: soc {
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +ranges = <0 0 0 0x>;
>> +compatible = "simple-bus";
>> +
>> +intc: interrupt-controller@17a0 {
>> +compatible = "arm,gic-v3";
>> +#address-cells = <1>;
>> +#size-cells = <1>;
>> +ranges;
>> +#interrupt-cells = <3>;
>> +interrupt-controller;
>> +#redistributor-regions = <1>;
>> +redistributor-stride = <0x0 0x2>;
>> +reg = <0x17a0 0x1>, /* GICD */
>> + <0x17a6 0x10>;/* GICR * 8 */
>> +interrupts = ;
>> +
>> +gic-its@17a4 {
>> +compatible = "arm,gic-v3-its";
>> +msi-controller;
>> +#msi-cells = <1>;
>> +reg = <0x17a4 0x2>;
>> +status = "disabled";
>> +};
>> +};
>> +
>> +gcc: clock-controller@10 {
>> +compatible = "qcom,gcc-sdm845";
>> +reg = <0x10 0x1f>;
>> +#clock-cells = <1>;
>> +#reset-cells = <1>;
>> +};
>> +
>> +tlmm: pinctrl@340 {
>> +compatible = "qcom,sdm845-pinctrl";
>> +reg = <0x0340 0xc0>;
>> +interrupts = ;
>
> Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC
> binding. Set it to the actual trigger value.
Thanks Marc for the review. I fixed these up and did a respin.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
hosted by The Linux Foundation
Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
Hi, On Mon, Feb 19, 2018 at 8:36 AM, Marc Zyngier wrote: >> + interrupts = ; > > Please do not use IRQ_TYPE_NONE, ever. It doesn't exist in the GIC > binding. Set it to the actual trigger value. > >> + interrupts = ; > > Same here. Thanks for the review Marc! Andy: If I'm reading everything correctly you're the one who would collect these patches and apply them. Is that right? Do they look OK to you in general? Would you prefer that Rajendra send out a v5 with the fixes pointed out by Marc, or would you prefer to fix them up yourself when applying? Is now a good time or would you prefer to wait? Thanks! :) -Doug
Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
On Fri, 16 Feb 2018 11:35:02 +0530
Rajendra Nayak wrote:
> Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
>
> Signed-off-by: Rajendra Nayak
> Reviewed-by: Doug Anderson
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++
> arch/arm64/boot/dts/qcom/sdm845.dtsi| 277
>
> 3 files changed, 293 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi
>
[...]
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> new file mode 100644
> index ..c46e726af621
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -0,0 +1,277 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * SDM845 SoC device tree source
> + *
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + memory@8000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0 0x8000 0 0>;
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo385";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo385";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + next-level-cache = <&L2_100>;
> + L2_100: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "qcom,kryo385";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + next-level-cache = <&L2_200>;
> + L2_200: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "qcom,kryo385";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + next-level-cache = <&L2_300>;
> + L2_300: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU4: cpu@400 {
> + device_type = "cpu";
> + compatible = "qcom,kryo385";
> + reg = <0x0 0x400>;
> + enable-method = "psci";
> + next-level-cache = <&L2_400>;
> + L2_400: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU5: cpu@500 {
> + device_type = "cpu";
> + compatible = "qcom,kryo385";
> + reg = <0x0 0x500>;
> + enable-method = "psci";
> + next-level-cache = <&L2_500>;
> + L2_500: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU6: cpu@600 {
> + device_type = "cpu";
> + compatible = "qcom,kryo385";
> + reg = <0x0 0x600>;
> + enable-method = "psci";
> + next-level-cache = <&L2_600>;
> + L2_600: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU7: cpu@700 {
> + device_type = "cpu";
> + compat
Re: [PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
Hi, On Thu, Feb 15, 2018 at 10:05 PM, Rajendra Nayak wrote: > Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files > > Signed-off-by: Rajendra Nayak > Reviewed-by: Doug Anderson > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++ > arch/arm64/boot/dts/qcom/sdm845.dtsi| 277 > > 3 files changed, 293 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts > create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/Makefile > b/arch/arm64/boot/dts/qcom/Makefile > index 55ec5ee7f7e8..9319e74b8906 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb > dtb-$(CONFIG_ARCH_QCOM)+= msm8992-bullhead-rev-101.dtb > dtb-$(CONFIG_ARCH_QCOM)+= msm8994-angler-rev-101.dtb > dtb-$(CONFIG_ARCH_QCOM)+= msm8996-mtp.dtb > +dtb-$(CONFIG_ARCH_QCOM)+= sdm845-mtp.dtb > diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > new file mode 100644 > index ..979ab49913f1 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > @@ -0,0 +1,15 @@ > +// SPDX-License-Identifier: GPL-2.0 This already has my Reviewed-by tag (and that's great), but just making it clear that I am in favor of this landing with just the GPL-2.0 license and not block waiting on the QC lawyers to hash out whether the device tree can really be dual-licensed. If lawyers come back soon then it will be easy to have a followup patch that changes this. Since (I don't think) any hobbyists have an SDM845 in their hands right now it seems unlikely to be hard to track down any authors in the meantime and make sure they're OK. If lawyers don't come back soon then it will be a good thing that we didn't block. Having this skeleton DTS file land sooner rather than later will unblock other patches to be sent out enabling other peripherals, which seems like a nice thing. :) -Doug
[PATCH v4 3/4] arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
Add a skeletal sdm845 SoC dtsi and MTP board dts/dtsi files
Signed-off-by: Rajendra Nayak
Reviewed-by: Doug Anderson
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 15 ++
arch/arm64/boot/dts/qcom/sdm845.dtsi| 277
3 files changed, 293 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sdm845-mtp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sdm845.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile
b/arch/arm64/boot/dts/qcom/Makefile
index 55ec5ee7f7e8..9319e74b8906 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM)+= msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM)+= msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM)+= msm8996-mtp.dtb
+dtb-$(CONFIG_ARCH_QCOM)+= sdm845-mtp.dtb
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
new file mode 100644
index ..979ab49913f1
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SDM845 MTP board device tree source
+ *
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sdm845.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM845 MTP";
+ compatible = "qcom,sdm845-mtp";
+};
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
new file mode 100644
index ..c46e726af621
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * SDM845 SoC device tree source
+ *
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ memory@8000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x8000 0 0>;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_300>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo385";
+ reg = <0x0 0x500>;
+
