[PATCH v4 3/9] ARM: dts: Add memory bus node for Exynos3250
This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has
following memory buses to translate data between DRAM and eMMC/sub-IPs.
Following list specifies the detailed relation between memory bus clock and DMC
IP in MIF (Memory Interface) block:
- DMC clock : DMC (Dynamic Memory Controller)
Following list specifies the detailed relation between memory bus clock and
sub-IPs in INT (Internal) block:
- ACLK100 clock : PERIL
- ACLK160 clock : LCD0
- ACLK200 clock : FSYS
- ACLK266 clock : ISP
- GDL/GDR clock : leftbus/rightbus
- SCLK_MFC clock : MFC
Cc: Kukjin Kim
Cc: Myungjoo Ham
Cc: Kyungmin Park
Signed-off-by: Chanwoo Choi
Acked-by: Kyungmin Park
Acked-by: Myungjoo Ham
---
arch/arm/boot/dts/exynos3250.dtsi | 125 ++
1 file changed, 125 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 9ed1260..3eaed53 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -99,6 +99,131 @@
};
};
+ memory_bus_mif: memory_bus@0 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 40 875000
+ 20 80
+ 133000 80
+ 10 80
+ 5 80>;
+ status = "disabled";
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = <_dmc CLK_DIV_DMC>;
+ clock-names = "memory-bus";
+ frequency = <
+ 40
+ 20
+ 133000
+ 10
+ 5>;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus@1 {
+ compatible = "samsung,exynos-memory-bus";
+
+ operating-points = <
+ 40 95
+ 20 95
+ 133000 925000
+ 10 85
+ 8 85
+ 5 85>;
+
+ status = "disabled";
+
+ blocks {
+ peril_block: memory_bus_block1 {
+ clocks = < CLK_DIV_ACLK_100>;
+ clock-names = "memory-bus";
+ frequency = <
+ 10
+ 10
+ 10
+ 10
+ 5
+ 5>;
+ };
+
+ lcd0_block: memory_bus_block2 {
+ clocks = < CLK_DIV_ACLK_160>;
+ clock-names = "memory-bus";
+ frequency = <
+ 20
+ 16
+ 10
+ 8
+ 8
+ 5>;
+ };
+
+ fsys_block: memory_bus_block3 {
+ clocks = < CLK_DIV_ACLK_200>;
+ clock-names = "memory-bus";
+ frequency = <
+ 20
+ 20
+ 10
+ 8
+ 5
+ 5>;
+ };
+
+ isp_block: memory_bus_block4 {
+ clocks = < CLK_DIV_ACLK_266>;
+ clock-names = "memory-bus";
+ frequency = <
+ 30
+ 20
+ 133000
+
[PATCH v4 3/9] ARM: dts: Add memory bus node for Exynos3250
This patch adds the memory bus node for Exynos3250 SoC. Exynos3250 has
following memory buses to translate data between DRAM and eMMC/sub-IPs.
Following list specifies the detailed relation between memory bus clock and DMC
IP in MIF (Memory Interface) block:
- DMC clock : DMC (Dynamic Memory Controller)
Following list specifies the detailed relation between memory bus clock and
sub-IPs in INT (Internal) block:
- ACLK100 clock : PERIL
- ACLK160 clock : LCD0
- ACLK200 clock : FSYS
- ACLK266 clock : ISP
- GDL/GDR clock : leftbus/rightbus
- SCLK_MFC clock : MFC
Cc: Kukjin Kim kg...@kernel.org
Cc: Myungjoo Ham myungjoo@samsung.com
Cc: Kyungmin Park kyungmin.p...@samsung.com
Signed-off-by: Chanwoo Choi cw00.c...@samsung.com
Acked-by: Kyungmin Park kyungmin.p...@samsung.com
Acked-by: Myungjoo Ham myungjoo@samsung.com
---
arch/arm/boot/dts/exynos3250.dtsi | 125 ++
1 file changed, 125 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi
b/arch/arm/boot/dts/exynos3250.dtsi
index 9ed1260..3eaed53 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -99,6 +99,131 @@
};
};
+ memory_bus_mif: memory_bus@0 {
+ compatible = samsung,exynos-memory-bus;
+
+ operating-points =
+ 40 875000
+ 20 80
+ 133000 80
+ 10 80
+ 5 80;
+ status = disabled;
+
+ blocks {
+ dmc_block: memory_bus_block1 {
+ clocks = cmu_dmc CLK_DIV_DMC;
+ clock-names = memory-bus;
+ frequency =
+ 40
+ 20
+ 133000
+ 10
+ 5;
+ };
+ };
+ };
+
+ memory_bus_int: memory_bus@1 {
+ compatible = samsung,exynos-memory-bus;
+
+ operating-points =
+ 40 95
+ 20 95
+ 133000 925000
+ 10 85
+ 8 85
+ 5 85;
+
+ status = disabled;
+
+ blocks {
+ peril_block: memory_bus_block1 {
+ clocks = cmu CLK_DIV_ACLK_100;
+ clock-names = memory-bus;
+ frequency =
+ 10
+ 10
+ 10
+ 10
+ 5
+ 5;
+ };
+
+ lcd0_block: memory_bus_block2 {
+ clocks = cmu CLK_DIV_ACLK_160;
+ clock-names = memory-bus;
+ frequency =
+ 20
+ 16
+ 10
+ 8
+ 8
+ 5;
+ };
+
+ fsys_block: memory_bus_block3 {
+ clocks = cmu CLK_DIV_ACLK_200;
+ clock-names = memory-bus;
+ frequency =
+ 20
+ 20
+ 10
+ 8
+ 5
+ 5;
+ };
+
+ isp_block: memory_bus_block4 {
+ clocks = cmu CLK_DIV_ACLK_266;
+ clock-names = memory-bus;
+ frequency =
+ 30
+
