Re: [PATCH v4 4/4] arm64: dts: sdm845: Add serial console support

[Doug Anderson]

Hi,

On Thu, Feb 15, 2018 at 10:05 PM, Rajendra Nayak  wrote:
> Add the qup uart node and geni se instance needed to
> support the serial console on the MTP.
>
> Signed-off-by: Rajendra Nayak 
> ---
>  arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 
> +
>  arch/arm64/boot/dts/qcom/sdm845.dtsi| 39 
> +
>  2 files changed, 78 insertions(+)

Looks nice to me.  Thanks!

As in your cover letter, this patch will almost certainly need to be
spun again because it's based on bindings that have review feedback.
For those of you playing along at home, see
.  Thus, I'm not
providing a Reviewed-by tag at the moemnt.

I will still say thanks for posting this (even though it was based on
old bindings) since it allowed us to make some good progress ahead of
time so we'll be very close to landing when the serial patch is spun
next.


In my ideal world the first 3 patches of this series would land sooner
rather than later and then this 4th patch would simply be re-posted on
its own when the bindings get more finalized (or, even better, if the
first 3 patches have landed then Karthikeyan could just glom this on
to the end of his next spin of the serial driver.  ;-)


-Doug

[PATCH v4 4/4] arm64: dts: sdm845: Add serial console support

[Rajendra Nayak]

Add the qup uart node and geni se instance needed to
support the serial console on the MTP.

Signed-off-by: Rajendra Nayak 
---
 arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 39 +
 arch/arm64/boot/dts/qcom/sdm845.dtsi| 39 +
 2 files changed, 78 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts 
b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index 979ab49913f1..2a1ed55b703e 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -12,4 +12,43 @@
 / {
model = "Qualcomm Technologies, Inc. SDM845 MTP";
compatible = "qcom,sdm845-mtp";
+
+   aliases {
+   serial0 = &qup_uart2;
+   };
+
+   chosen {
+   stdout-path = "serial0";
+   };
+};
+
+&soc {
+   geni-se@ac {
+   serial@a84000 {
+   status = "okay";
+   };
+   };
+
+   pinctrl@340 {
+   qup-uart2-default {
+   pinconf_tx {
+   pins = "gpio4";
+   drive-strength = <2>;
+   bias-disable;
+   };
+
+   pinconf_rx {
+   pins = "gpio5";
+   drive-strength = <2>;
+   bias-pull-up;
+   };
+   };
+
+   qup-uart2-sleep {
+   pinconf {
+   pins = "gpio4", "gpio5";
+   bias-pull-down;
+   };
+   };
+   };
 };
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi 
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index c46e726af621..7b5c16eb63b7 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include 
+#include 
 
 / {
interrupt-parent = <&intc>;
@@ -195,6 +196,20 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
+
+   qup_uart2_default: qup-uart2-default {
+   pinmux {
+   function = "qup9";
+   pins = "gpio4", "gpio5";
+   };
+   };
+
+   qup_uart2_sleep: qup-uart2-sleep {
+   pinmux {
+   function = "gpio";
+   pins = "gpio4", "gpio5";
+   };
+   };
};
 
timer@17c9 {
@@ -273,5 +288,29 @@
#interrupt-cells = <4>;
cell-index = <0>;
};
+
+   geni-se@ac {
+   compatible = "qcom,geni-se-qup";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+   reg = <0xac 0x6000>;
+   clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+   clock-names = "m-ahb", "s-ahb";
+
+   qup_uart2: serial@a84000 {
+   compatible = "qcom,geni-debug-uart";
+   reg = <0xa84000 0x4000>;
+   reg-names = "se-phys";
+   clock-names = "se-clk";
+   clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+   pinctrl-names = "default", "sleep";
+   pinctrl-0 = <&qup_uart2_default>;
+   pinctrl-1 = <&qup_uart2_sleep>;
+   interrupts = ;
+   status = "disabled";
+   };
+   };
};
 };
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