Re: [PATCH v4 5/5] clk: qcom: gcc: Add clock driver for SM8350

[Bjorn Andersson]

On Sun 17 Jan 22:43 CST 2021, Vinod Koul wrote:

> From: Vivek Aknurwar 
> 
> This adds Global Clock controller (GCC) driver for SM8350 SoC
> 
> Signed-off-by: Vivek Aknurwar 
> Signed-off-by: Jeevan Shriram 
> [vkoul: rebase and tidy up for upstream]
> Signed-off-by: Vinod Koul 

Reviewed-by: Bjorn Andersson 

Regards,
Bjorn

> ---
>  drivers/clk/qcom/Kconfig  |8 +
>  drivers/clk/qcom/Makefile |1 +
>  drivers/clk/qcom/gcc-sm8350.c | 3790 +
>  3 files changed, 3799 insertions(+)
>  create mode 100644 drivers/clk/qcom/gcc-sm8350.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index d32bb12cd8d0..54b217956469 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -454,6 +454,14 @@ config SM_GCC_8250
> Say Y if you want to use peripheral devices such as UART,
> SPI, I2C, USB, SD/UFS, PCIe etc.
>  
> +config SM_GCC_8350
> + tristate "SM8350 Global Clock Controller"
> + select QCOM_GDSC
> + help
> +   Support for the global clock controller on SM8350 devices.
> +   Say Y if you want to use peripheral devices such as UART,
> +   SPI, I2C, USB, SD/UFS, PCIe etc.
> +
>  config SM_GPUCC_8150
>   tristate "SM8150 Graphics Clock Controller"
>   select SM_GCC_8150
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 9e5e0e3cb7b4..a89c7016 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -70,6 +70,7 @@ obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
>  obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
>  obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
>  obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
> +obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
>  obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
>  obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
>  obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
> diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
> new file mode 100644
> index ..a16c08651206
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-sm8350.c
> @@ -0,0 +1,3790 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2020-2021, Linaro Limited
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-branch.h"
> +#include "clk-rcg.h"
> +#include "clk-regmap.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "reset.h"
> +
> +enum {
> + P_BI_TCXO,
> + P_CORE_BI_PLL_TEST_SE,
> + P_GCC_GPLL0_OUT_EVEN,
> + P_GCC_GPLL0_OUT_MAIN,
> + P_GCC_GPLL4_OUT_MAIN,
> + P_GCC_GPLL9_OUT_MAIN,
> + P_PCIE_0_PIPE_CLK,
> + P_PCIE_1_PIPE_CLK,
> + P_SLEEP_CLK,
> + P_UFS_CARD_RX_SYMBOL_0_CLK,
> + P_UFS_CARD_RX_SYMBOL_1_CLK,
> + P_UFS_CARD_TX_SYMBOL_0_CLK,
> + P_UFS_PHY_RX_SYMBOL_0_CLK,
> + P_UFS_PHY_RX_SYMBOL_1_CLK,
> + P_UFS_PHY_TX_SYMBOL_0_CLK,
> + P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
> + P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
> +};
> +
> +static struct clk_alpha_pll gcc_gpll0 = {
> + .offset = 0x0,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> + .clkr = {
> + .enable_reg = 0x52018,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpll0",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "bi_tcxo",
> + },
> + .num_parents = 1,
> + .ops = _alpha_pll_fixed_lucid_5lpe_ops,
> + },
> + },
> +};
> +
> +static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
> + { 0x1, 2 },
> + { }
> +};
> +
> +static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
> + .offset = 0x0,
> + .post_div_shift = 8,
> + .post_div_table = post_div_table_gcc_gpll0_out_even,
> + .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
> + .width = 4,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "gcc_gpll0_out_even",
> + .parent_data = &(const struct clk_parent_data){
> + .hw = _gpll0.clkr.hw,
> + },
> + .num_parents = 1,
> + .ops = _alpha_pll_postdiv_lucid_5lpe_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll gcc_gpll4 = {
> + .offset = 0x76000,
> + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
> + .clkr = {
> + .enable_reg = 0x52018,
> + .enable_mask = BIT(4),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpll4",
> + .parent_data = &(const struct clk_parent_data){
> + .fw_name = "bi_tcxo",
> +  

[PATCH v4 5/5] clk: qcom: gcc: Add clock driver for SM8350

[Vinod Koul]

From: Vivek Aknurwar 

This adds Global Clock controller (GCC) driver for SM8350 SoC

Signed-off-by: Vivek Aknurwar 
Signed-off-by: Jeevan Shriram 
[vkoul: rebase and tidy up for upstream]
Signed-off-by: Vinod Koul 
---
 drivers/clk/qcom/Kconfig  |8 +
 drivers/clk/qcom/Makefile |1 +
 drivers/clk/qcom/gcc-sm8350.c | 3790 +
 3 files changed, 3799 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-sm8350.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index d32bb12cd8d0..54b217956469 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -454,6 +454,14 @@ config SM_GCC_8250
  Say Y if you want to use peripheral devices such as UART,
  SPI, I2C, USB, SD/UFS, PCIe etc.
 
+config SM_GCC_8350
+   tristate "SM8350 Global Clock Controller"
+   select QCOM_GDSC
+   help
+ Support for the global clock controller on SM8350 devices.
+ Say Y if you want to use peripheral devices such as UART,
+ SPI, I2C, USB, SD/UFS, PCIe etc.
+
 config SM_GPUCC_8150
tristate "SM8150 Graphics Clock Controller"
select SM_GCC_8150
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 9e5e0e3cb7b4..a89c7016 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -70,6 +70,7 @@ obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
 obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
 obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
 obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
+obj-$(CONFIG_SM_GCC_8350) += gcc-sm8350.o
 obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
 obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
 obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
diff --git a/drivers/clk/qcom/gcc-sm8350.c b/drivers/clk/qcom/gcc-sm8350.c
new file mode 100644
index ..a16c08651206
--- /dev/null
+++ b/drivers/clk/qcom/gcc-sm8350.c
@@ -0,0 +1,3790 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, Linaro Limited
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "reset.h"
+
+enum {
+   P_BI_TCXO,
+   P_CORE_BI_PLL_TEST_SE,
+   P_GCC_GPLL0_OUT_EVEN,
+   P_GCC_GPLL0_OUT_MAIN,
+   P_GCC_GPLL4_OUT_MAIN,
+   P_GCC_GPLL9_OUT_MAIN,
+   P_PCIE_0_PIPE_CLK,
+   P_PCIE_1_PIPE_CLK,
+   P_SLEEP_CLK,
+   P_UFS_CARD_RX_SYMBOL_0_CLK,
+   P_UFS_CARD_RX_SYMBOL_1_CLK,
+   P_UFS_CARD_TX_SYMBOL_0_CLK,
+   P_UFS_PHY_RX_SYMBOL_0_CLK,
+   P_UFS_PHY_RX_SYMBOL_1_CLK,
+   P_UFS_PHY_TX_SYMBOL_0_CLK,
+   P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
+   P_USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK,
+};
+
+static struct clk_alpha_pll gcc_gpll0 = {
+   .offset = 0x0,
+   .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+   .clkr = {
+   .enable_reg = 0x52018,
+   .enable_mask = BIT(0),
+   .hw.init = &(struct clk_init_data){
+   .name = "gcc_gpll0",
+   .parent_data = &(const struct clk_parent_data){
+   .fw_name = "bi_tcxo",
+   },
+   .num_parents = 1,
+   .ops = _alpha_pll_fixed_lucid_5lpe_ops,
+   },
+   },
+};
+
+static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
+   { 0x1, 2 },
+   { }
+};
+
+static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
+   .offset = 0x0,
+   .post_div_shift = 8,
+   .post_div_table = post_div_table_gcc_gpll0_out_even,
+   .num_post_div = ARRAY_SIZE(post_div_table_gcc_gpll0_out_even),
+   .width = 4,
+   .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+   .clkr.hw.init = &(struct clk_init_data){
+   .name = "gcc_gpll0_out_even",
+   .parent_data = &(const struct clk_parent_data){
+   .hw = _gpll0.clkr.hw,
+   },
+   .num_parents = 1,
+   .ops = _alpha_pll_postdiv_lucid_5lpe_ops,
+   },
+};
+
+static struct clk_alpha_pll gcc_gpll4 = {
+   .offset = 0x76000,
+   .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+   .clkr = {
+   .enable_reg = 0x52018,
+   .enable_mask = BIT(4),
+   .hw.init = &(struct clk_init_data){
+   .name = "gcc_gpll4",
+   .parent_data = &(const struct clk_parent_data){
+   .fw_name = "bi_tcxo",
+   .name = "bi_tcxo",
+   },
+   .num_parents = 1,
+   .ops = _alpha_pll_fixed_lucid_5lpe_ops,
+   },
+   },
+};
+
+static struct clk_alpha_pll gcc_gpll9 = {
+