Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
Notes:
v4:
- fixed copyright headers according to license-rules.rst
- removed comments from clock bindings
v3:
- added hypervisor-related apertures to GIC node
- removed GPL boilerplate in favor of SPDX and harmonized
copyright headers
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 344 +
include/dt-bindings/clock/tegra194-clock.h | 321 +++
include/dt-bindings/gpio/tegra194-gpio.h | 61 +
include/dt-bindings/power/tegra194-powergate.h | 35 +++
include/dt-bindings/reset/tegra194-reset.h | 152 +++
5 files changed, 913 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra194.dtsi
create mode 100644 include/dt-bindings/clock/tegra194-clock.h
create mode 100644 include/dt-bindings/gpio/tegra194-gpio.h
create mode 100644 include/dt-bindings/power/tegra194-powergate.h
create mode 100644 include/dt-bindings/reset/tegra194-reset.h
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
new file mode 100644
index ..6322ef265c2f
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "nvidia,tegra194";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* control backbone */
+ cbb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x0 0x4000>;
+
+ uarta: serial@310 {
+ compatible = "nvidia,tegra194-uart",
"nvidia,tegra20-uart";
+ reg = <0x0310 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTA>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTA>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartb: serial@311 {
+ compatible = "nvidia,tegra194-uart",
"nvidia,tegra20-uart";
+ reg = <0x0311 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTB>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTB>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartd: serial@313 {
+ compatible = "nvidia,tegra194-uart",
"nvidia,tegra20-uart";
+ reg = <0x0313 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTD>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTD>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uarte: serial@314 {
+ compatible = "nvidia,tegra194-uart",
"nvidia,tegra20-uart";
+ reg = <0x0314 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTE>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTE>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartf: serial@315 {
+ compatible = "nvidia,tegra194-uart",
"nvidia,tegra20-uart";
+ reg = <0x0315 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTF>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTF>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ gen1_i2c: i2c@316 {
+ compatible = "nvidia,tegra194-i2c",
"nvidia,tegra114-i2c";
+ reg = <0x0316 0x1>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C1>;
+ clock-names = "div-clk";
+
