[PATCH v4 7/7] dt-bindings: PCI: add support for mt2712 and mt7622

[honghui.zhang]

From: Ryder Lee 

Add controller support for mt2712/mt7622 and update related
properities.

Signed-off-by: Ryder Lee 
Signed-off-by: Honghui Zhang 
Acked-by: Rob Herring 
---
 .../devicetree/bindings/pci/mediatek-pcie.txt  | 168 -
 1 file changed, 161 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt 
b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
index 0fdcb15..2e81742 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -3,18 +3,31 @@ MediaTek Gen2 PCIe controller
 Required properties:
 - compatible: Should contain one of the following strings:
"mediatek,mt2701-pcie"
+   "mediatek,mt2712-pcie"
+   "mediatek,mt7622-pcie"
"mediatek,mt7623-pcie"
 - device_type: Must be "pci"
-- reg: Base addresses and lengths of the PCIe controller.
+- reg: Base addresses and lengths of the PCIe subsys and root ports.
+- reg-names: Names of the above areas to use during resource look-up.
 - #address-cells: Address representation for root ports (must be 3)
 - #size-cells: Size representation for root ports (must be 2)
 - clocks: Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
-  - free_ck :for reference clock of PCIe subsys
-  - sys_ck0 :for clock of Port0
-  - sys_ck1 :for clock of Port1
-  - sys_ck2 :for clock of Port2
+- clock-names:
+  Mandatory entries:
+   - sys_ckN :transaction layer and data link layer clock
+  Required entries for MT2701/MT7623:
+   - free_ck :for reference clock of PCIe subsys
+  Required entries for MT2712/MT7622:
+   - ahb_ckN :AHB slave interface operating clock for CSR access and RC
+ initiated MMIO access
+  Required entries for MT7622:
+   - axi_ckN :application layer MMIO channel operating clock
+   - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
+ pcie_mac_ck/pcie_pipe_ck is turned off
+   - obff_ckN :OBFF functional block operating clock
+   - pipe_ckN :LTSSM and PHY/MAC layer operating clock
+  where N starting from 0 to one less than the number of root ports.
 - phys: List of PHY specifiers (used by generic PHY framework).
 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
   number of PHYs as specified in *phys* property.
@@ -33,6 +46,10 @@ Required properties for MT7623/MT2701:
 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
   number of root ports.
 
+Required properties for MT2712/MT7622:
+-interrupts: A list of interrupt outputs of the controller, must have one
+entry for each PCIe port
+
 In addition, the device tree node must have sub-nodes describing each
 PCIe port interface, having the following mandatory properties:
 
@@ -50,7 +67,7 @@ Required properties:
   property is sufficient.
 - num-lanes: Number of lanes to use for this port.
 
-Examples:
+Examples for MT7623:
 
hifsys: syscon@1a00 {
compatible = "mediatek,mt7623-hifsys",
@@ -68,6 +85,7 @@ Examples:
  <0 0x1a142000 0 0x1000>, /* Port0 registers */
  <0 0x1a143000 0 0x1000>, /* Port1 registers */
  <0 0x1a144000 0 0x1000>; /* Port2 registers */
+   reg-names = "subsys", "port0", "port1", "port2";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
@@ -128,3 +146,139 @@ Examples:
num-lanes = <1>;
};
};
+
+Examples for MT2712:
+   pcie: pcie@1170 {
+   compatible = "mediatek,mt2712-pcie";
+   device_type = "pci";
+   reg = <0 0x1170 0 0x1000>,
+ <0 0x112ff000 0 0x1000>;
+   reg-names = "port0", "port1";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   interrupts = ,
+;
+   clocks = < CLK_TOP_PE2_MAC_P0_SEL>,
+< CLK_TOP_PE2_MAC_P1_SEL>,
+< CLK_PERI_PCIE0>,
+< CLK_PERI_PCIE1>;
+   clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+   phys = <_phy PHY_TYPE_PCIE>, <_phy PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy0", "pcie-phy1";
+   bus-range = <0x00 0xff>;
+   ranges = <0x8200 0 0x2000  0x0 0x2000  0 
0x1000>;
+
+   pcie0: pcie@0,0 {
+   device_type = "pci";
+   reg = <0x 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges;
+   

[PATCH v4 7/7] dt-bindings: PCI: add support for mt2712 and mt7622

[honghui.zhang]

From: Ryder Lee 

Add controller support for mt2712/mt7622 and update related
properities.

Signed-off-by: Ryder Lee 
Signed-off-by: Honghui Zhang 
Acked-by: Rob Herring 
---
 .../devicetree/bindings/pci/mediatek-pcie.txt  | 168 -
 1 file changed, 161 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt 
b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
index 0fdcb15..2e81742 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
@@ -3,18 +3,31 @@ MediaTek Gen2 PCIe controller
 Required properties:
 - compatible: Should contain one of the following strings:
"mediatek,mt2701-pcie"
+   "mediatek,mt2712-pcie"
+   "mediatek,mt7622-pcie"
"mediatek,mt7623-pcie"
 - device_type: Must be "pci"
-- reg: Base addresses and lengths of the PCIe controller.
+- reg: Base addresses and lengths of the PCIe subsys and root ports.
+- reg-names: Names of the above areas to use during resource look-up.
 - #address-cells: Address representation for root ports (must be 3)
 - #size-cells: Size representation for root ports (must be 2)
 - clocks: Must contain an entry for each entry in clock-names.
   See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
-  - free_ck :for reference clock of PCIe subsys
-  - sys_ck0 :for clock of Port0
-  - sys_ck1 :for clock of Port1
-  - sys_ck2 :for clock of Port2
+- clock-names:
+  Mandatory entries:
+   - sys_ckN :transaction layer and data link layer clock
+  Required entries for MT2701/MT7623:
+   - free_ck :for reference clock of PCIe subsys
+  Required entries for MT2712/MT7622:
+   - ahb_ckN :AHB slave interface operating clock for CSR access and RC
+ initiated MMIO access
+  Required entries for MT7622:
+   - axi_ckN :application layer MMIO channel operating clock
+   - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
+ pcie_mac_ck/pcie_pipe_ck is turned off
+   - obff_ckN :OBFF functional block operating clock
+   - pipe_ckN :LTSSM and PHY/MAC layer operating clock
+  where N starting from 0 to one less than the number of root ports.
 - phys: List of PHY specifiers (used by generic PHY framework).
 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
   number of PHYs as specified in *phys* property.
@@ -33,6 +46,10 @@ Required properties for MT7623/MT2701:
 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
   number of root ports.
 
+Required properties for MT2712/MT7622:
+-interrupts: A list of interrupt outputs of the controller, must have one
+entry for each PCIe port
+
 In addition, the device tree node must have sub-nodes describing each
 PCIe port interface, having the following mandatory properties:
 
@@ -50,7 +67,7 @@ Required properties:
   property is sufficient.
 - num-lanes: Number of lanes to use for this port.
 
-Examples:
+Examples for MT7623:
 
hifsys: syscon@1a00 {
compatible = "mediatek,mt7623-hifsys",
@@ -68,6 +85,7 @@ Examples:
  <0 0x1a142000 0 0x1000>, /* Port0 registers */
  <0 0x1a143000 0 0x1000>, /* Port1 registers */
  <0 0x1a144000 0 0x1000>; /* Port2 registers */
+   reg-names = "subsys", "port0", "port1", "port2";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
@@ -128,3 +146,139 @@ Examples:
num-lanes = <1>;
};
};
+
+Examples for MT2712:
+   pcie: pcie@1170 {
+   compatible = "mediatek,mt2712-pcie";
+   device_type = "pci";
+   reg = <0 0x1170 0 0x1000>,
+ <0 0x112ff000 0 0x1000>;
+   reg-names = "port0", "port1";
+   #address-cells = <3>;
+   #size-cells = <2>;
+   interrupts = ,
+;
+   clocks = < CLK_TOP_PE2_MAC_P0_SEL>,
+< CLK_TOP_PE2_MAC_P1_SEL>,
+< CLK_PERI_PCIE0>,
+< CLK_PERI_PCIE1>;
+   clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
+   phys = <_phy PHY_TYPE_PCIE>, <_phy PHY_TYPE_PCIE>;
+   phy-names = "pcie-phy0", "pcie-phy1";
+   bus-range = <0x00 0xff>;
+   ranges = <0x8200 0 0x2000  0x0 0x2000  0 
0x1000>;
+
+   pcie0: pcie@0,0 {
+   device_type = "pci";
+   reg = <0x 0 0 0 0>;
+   #address-cells = <3>;
+   #size-cells = <2>;
+   #interrupt-cells = <1>;
+   ranges;
+   num-lanes = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+