[PATCH v4 9/9] arm: dts: genmai: Add ethernet pin group
Add pin configuration subnode for ETHER ethernet controller. Signed-off-by: Jacopo Mondi--- arch/arm/boot/dts/r7s72100-genmai.dts | 41 +++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index f7c512e..328f4c9 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -63,6 +63,34 @@ pinmux = , ; bi-directional; }; + + ether_pins: ether { + pins { + /* Ethernet on Ports 1,2,3,5 */ + pinmux = ,/* P1_14 = ET_COL */ + , /* P5_9 = ET_MDC */ + , /* P3_4 = ET_RXCLK */ + , /* P3_5 = ET_RXER */ + , /* P3_6 = ET_RXDV */ + , /* P2_0 = ET_TXCLK */ + , /* P2_1 = ET_TXER */ + , /* P2_2 = ET_TXEN */ + , /* P2_3 = ET_CRS */ + , /* P2_4 = ET_TXD0 */ + , /* P2_5 = ET_TXD1 */ + , /* P2_6 = ET_TXD2 */ + , /* P2_7 = ET_TXD3 */ + , /* P2_8 = ET_RXD0 */ + , /* P2_9 = ET_RXD1 */ + ,/* P2_10 = ET_RXD2 */ + ;/* P2_11 = ET_RXD3 */ + }; + + pins_bidir { + pinmux = ;/* P3_3 = ET_MDIO */ + bi-directional; + }; + }; }; _clk { @@ -77,6 +105,19 @@ status = "okay"; }; + { + pinctrl-names = "default"; + pinctrl-0 = <_pins>; + + status = "okay"; + + renesas,no-ether-link; + phy-handle = <>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + { status = "okay"; clock-frequency = <40>; -- 2.7.4
[PATCH v4 9/9] arm: dts: genmai: Add ethernet pin group
Add pin configuration subnode for ETHER ethernet controller. Signed-off-by: Jacopo Mondi --- arch/arm/boot/dts/r7s72100-genmai.dts | 41 +++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index f7c512e..328f4c9 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -63,6 +63,34 @@ pinmux = , ; bi-directional; }; + + ether_pins: ether { + pins { + /* Ethernet on Ports 1,2,3,5 */ + pinmux = ,/* P1_14 = ET_COL */ +, /* P5_9 = ET_MDC */ +, /* P3_4 = ET_RXCLK */ +, /* P3_5 = ET_RXER */ +, /* P3_6 = ET_RXDV */ +, /* P2_0 = ET_TXCLK */ +, /* P2_1 = ET_TXER */ +, /* P2_2 = ET_TXEN */ +, /* P2_3 = ET_CRS */ +, /* P2_4 = ET_TXD0 */ +, /* P2_5 = ET_TXD1 */ +, /* P2_6 = ET_TXD2 */ +, /* P2_7 = ET_TXD3 */ +, /* P2_8 = ET_RXD0 */ +, /* P2_9 = ET_RXD1 */ +,/* P2_10 = ET_RXD2 */ +;/* P2_11 = ET_RXD3 */ + }; + + pins_bidir { + pinmux = ;/* P3_3 = ET_MDIO */ + bi-directional; + }; + }; }; _clk { @@ -77,6 +105,19 @@ status = "okay"; }; + { + pinctrl-names = "default"; + pinctrl-0 = <_pins>; + + status = "okay"; + + renesas,no-ether-link; + phy-handle = <>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + { status = "okay"; clock-frequency = <40>; -- 2.7.4