Re: [PATCH v5] clk: rockchip: disable unused clocks

2014-11-04 Thread Heiko Stübner 
Hi Kever,

Am Dienstag, 4. November 2014, 17:11:10 schrieb Kever Yang:
> The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
> all the clocks are available like default power on state.
> We have implement the clock manage in most of rockchip drivers,
> it is time to remove it for power save.
> Instead we add CLK_IGNORE_UNUSED for some clock nodes which should
> be on during boot or no module driver in kernel will initialize it.
> 
> Signed-off-by: Kever Yang 
> Reviewed-by: Doug Anderson 
> Tested-by: Doug Anderson 

I applied this with some slight modifications.
- it seemed to be based on your dclk_ops series - fixed that
- remove the flag from the uart2 on the cortex-a9 too
- let DCLK_VOPx and HCLK_VOPx be autodisabled on rk3288
  [tested by Doug]


Heiko
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Re: [PATCH v5] clk: rockchip: disable unused clocks

2014-11-04 Thread Doug Anderson 
Kever,

On Tue, Nov 4, 2014 at 1:11 AM, Kever Yang  wrote:
> The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
> all the clocks are available like default power on state.
> We have implement the clock manage in most of rockchip drivers,
> it is time to remove it for power save.
> Instead we add CLK_IGNORE_UNUSED for some clock nodes which should
> be on during boot or no module driver in kernel will initialize it.
>
> Signed-off-by: Kever Yang 
> Reviewed-by: Doug Anderson 
> Tested-by: Doug Anderson 
> ---
>
> Changes in v5:
> - take CLK_IGNORE_UNUSED tag out of EMMC and UART2
> - take CLK_IGNORE_UNUSED tag out of pclk_publ*, pclk_ddrupctl*
> - add Doug's Reviewed-by and Tested-by

You also took CLK_IGNORE_UNUSED out of dclk_vop0.  I don't have a
problem with that since my test cases still work and I'm all for
removing as many of these as we can.


> Changes in v4:
> - add CLK_IGNORE_UNUSED tag for all the niu/arbi/matrix clock
>
> Changes in v3:
> - get CLK_DIVIDER_READ_ONLY tag back fro armcores
> - add CLK_IGNORE_UNUSED tag for cs_dbg, pclk_dgb_pre and pclk_rkpwm
>
> Changes in v2:
> - get some clock ID back
> - add CLK_IGNORE_UNUSED tag for aclk_strc and aclk_core in clk-rk3188.c
> - add CLK_IGNORE_UNUSED tag for rk3288 dwc2
>
>  drivers/clk/rockchip/clk-rk3188.c |  40 ++--
>  drivers/clk/rockchip/clk-rk3288.c | 132 
> +++---
>  drivers/clk/rockchip/clk.c|   9 ---
>  3 files changed, 86 insertions(+), 95 deletions(-)

For whatever reason this patch didn't apply super cleanly.  Maybe you
have other local patches to these files that you didn't send up?  It's
nice to post a patch directly atop some upstream tree.  I get:

fatal: sha1 information is lacking or useless
(drivers/clk/rockchip/clk-rk3288.c).
Repository lacks necessary blobs to fall back on 3-way merge.
Cannot fall back to three-way merge.

...but "patch -p1 < x" had no trouble applying for me...
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[PATCH v5] clk: rockchip: disable unused clocks

2014-11-04 Thread Kever Yang 
The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
all the clocks are available like default power on state.
We have implement the clock manage in most of rockchip drivers,
it is time to remove it for power save.
Instead we add CLK_IGNORE_UNUSED for some clock nodes which should
be on during boot or no module driver in kernel will initialize it.

Signed-off-by: Kever Yang 
Reviewed-by: Doug Anderson 
Tested-by: Doug Anderson 
---

Changes in v5:
- take CLK_IGNORE_UNUSED tag out of EMMC and UART2
- take CLK_IGNORE_UNUSED tag out of pclk_publ*, pclk_ddrupctl*
- add Doug's Reviewed-by and Tested-by

Changes in v4:
- add CLK_IGNORE_UNUSED tag for all the niu/arbi/matrix clock

Changes in v3:
- get CLK_DIVIDER_READ_ONLY tag back fro armcores
- add CLK_IGNORE_UNUSED tag for cs_dbg, pclk_dgb_pre and pclk_rkpwm

Changes in v2:
- get some clock ID back
- add CLK_IGNORE_UNUSED tag for aclk_strc and aclk_core in clk-rk3188.c
- add CLK_IGNORE_UNUSED tag for rk3288 dwc2

 drivers/clk/rockchip/clk-rk3188.c |  40 ++--
 drivers/clk/rockchip/clk-rk3288.c | 132 +++---
 drivers/clk/rockchip/clk.c|   9 ---
 3 files changed, 86 insertions(+), 95 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3188.c 
b/drivers/clk/rockchip/clk-rk3188.c
index beed49c..1800cfe 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -257,9 +257,9 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(0, "hclk_vdpu", "aclk_vdpu", 0,
RK2928_CLKGATE_CON(3), 12, GFLAGS),
 
-   GATE(0, "gpll_ddr", "gpll", 0,
+   GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 7, GFLAGS),
-   COMPOSITE(0, "ddrphy", mux_ddrphy_p, 0,
+   COMPOSITE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | 
CLK_DIVIDER_POWER_OF_TWO,
RK2928_CLKGATE_CON(0), 2, GFLAGS),
 
@@ -270,10 +270,10 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
RK2928_CLKGATE_CON(0), 6, GFLAGS),
GATE(0, "pclk_cpu", "pclk_cpu_pre", 0,
RK2928_CLKGATE_CON(0), 5, GFLAGS),
-   GATE(0, "hclk_cpu", "hclk_cpu_pre", 0,
+   GATE(0, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(0), 4, GFLAGS),
 
-   COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 0,
+   COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, 
CLK_IGNORE_UNUSED,
RK2928_CLKSEL_CON(31), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 0, GFLAGS),
COMPOSITE(0, "aclk_lcdc1_pre", mux_pll_src_cpll_gpll_p, 0,
@@ -304,9 +304,9 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 * the 480m are generated inside the usb block from these clocks,
 * but they are also a source for the hsicphy clock.
 */
-   GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", 0,
+   GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
-   GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", 0,
+   GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 6, GFLAGS),
 
COMPOSITE(0, "mac_src", mux_mac_p, 0,
@@ -399,8 +399,8 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
 
/* aclk_cpu gates */
GATE(ACLK_DMA1, "aclk_dma1", "aclk_cpu", 0, RK2928_CLKGATE_CON(5), 0, 
GFLAGS),
-   GATE(0, "aclk_intmem", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 12, 
GFLAGS),
-   GATE(0, "aclk_strc_sys", "aclk_cpu", 0, RK2928_CLKGATE_CON(4), 10, 
GFLAGS),
+   GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 12, GFLAGS),
+   GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 10, GFLAGS),
 
/* hclk_cpu gates */
GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, 
GFLAGS),
@@ -416,8 +416,8 @@ static struct rockchip_clk_branch common_clk_branches[] 
__initdata = {
GATE(HCLK_RGA, "hclk_rga", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 10, 
GFLAGS),
 
/* hclk_peri gates */
-   GATE(0, "hclk_peri_axi_matrix", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 
0, GFLAGS),
-   GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 6, 
GFLAGS),
+   GATE(0, "hclk_peri_axi_matrix", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 0, GFLAGS),
+   GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, 
RK2928_CLKGATE_CON(4), 6, GFLAGS),
GATE(0, "hclk_emem_peri", "hclk_peri", 0, RK2928_CLKGATE_CON(4), 7, 
GFLAGS),
GATE(HCLK_EMAC, "hclk_emac", "hclk_peri", 0, RK2928_CLKGATE_CON(7), 0, 
GFLAGS),
GATE(HCLK_NANDC0, "hclk_