On Mon, Jul 11, 2016 at 05:06:57PM -0700, Bin Gao wrote:
> This patch introduces a separate GPIO driver for Intel WhiskeyCove PMIC.
> This driver is based on gpio-crystalcove.c.
>
> Signed-off-by: Ajay Thomas
> Signed-off-by: Bin Gao
I have a couple of comments below. Once you have addressed those you can
add my,
Reviewed-by: Mika Westerberg
> ---
> Changes in v5:
> - Revisited the interrupt handler code to iterate until all pending
>interrupts are handled. This change is to avoid missing interrupt
>when we're inside the interrupt handler.
> - Used regmap_bulk_read() to read address adjacent registers.
> Changes in v4:
> - Converted CTLI_INTCNT_XX macros to less verbose ones INT_DETECT_XX.
> - Add comments about why there is no .pm for the driver.
> - Header files re-ordered.
> - Various coding style change to address Andy's comments.
> Changes in v3:
> - Fixed the year in copyright line(2015-->2016).
> - Removed DRV_NAME macro.
> - Added kernel-doc for regmap_irq_chip of the wcove_gpio structure.
> - Line length fix.
> Changes in v2:
> - Typo fix (Whsikey --> Whiskey).
> - Included linux/gpio/driver.h instead of linux/gpio.h
> - Implemented .set_single_ended().
> - Added GPIO register description.
> - Replaced container_of() with gpiochip_get_data().
> - Removed unnecessary "if (gpio > WCOVE_VGPIO_NUM" check.
> - Removed the device id table and added MODULE_ALIAS().
> drivers/gpio/Kconfig | 13 ++
> drivers/gpio/Makefile | 1 +
> drivers/gpio/gpio-wcove.c | 444
> ++
> 3 files changed, 458 insertions(+)
> create mode 100644 drivers/gpio/gpio-wcove.c
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 536112f..0f33982 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -806,6 +806,19 @@ config GPIO_CRYSTAL_COVE
> This driver can also be built as a module. If so, the module will be
> called gpio-crystalcove.
>
> +config GPIO_WHISKEY_COVE
> + tristate "GPIO support for Whiskey Cove PMIC"
> + depends on INTEL_SOC_PMIC
> + select GPIOLIB_IRQCHIP
> + help
> + Support for GPIO pins on Whiskey Cove PMIC.
> +
> + Say Yes if you have a Intel SoC based tablet with Whiskey Cove PMIC
> + inside.
> +
> + This driver can also be built as a module. If so, the module will be
> + called gpio-wcove.
> +
> config GPIO_CS5535
> tristate "AMD CS5535/CS5536 GPIO support"
> depends on MFD_CS5535
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 991598e..fff6914 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -34,6 +34,7 @@ obj-$(CONFIG_GPIO_BT8XX)+= gpio-bt8xx.o
> obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o
> obj-$(CONFIG_GPIO_CS5535)+= gpio-cs5535.o
> obj-$(CONFIG_GPIO_CRYSTAL_COVE) += gpio-crystalcove.o
> +obj-$(CONFIG_GPIO_WHISKEY_COVE) += gpio-wcove.o
> obj-$(CONFIG_GPIO_DA9052)+= gpio-da9052.o
> obj-$(CONFIG_GPIO_DA9055)+= gpio-da9055.o
> obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
> diff --git a/drivers/gpio/gpio-wcove.c b/drivers/gpio/gpio-wcove.c
> new file mode 100644
> index 000..e29e5a9
> --- /dev/null
> +++ b/drivers/gpio/gpio-wcove.c
> @@ -0,0 +1,444 @@
> +/*
> + * gpio-wcove.c - Intel Whiskey Cove GPIO Driver
> + *
> + * This driver is written based on gpio-crystalcove.c
> + *
> + * Copyright (C) 2016 Intel Corporation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License version
> + * 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/*
> + * Whiskey Cove PMIC has 13 physical GPIO pins divided into 3 banks:
> + * Bank 0: Pin 0 - 6
> + * Bank 1: Pin 7 - 10
> + * Bank 2: Pin 11 -12
> + * Each pin has one output control register and one input control register.
> + */
> +#define BANK0_NR_PINS7
> +#define BANK1_NR_PINS4
> +#define BANK2_NR_PINS2
> +#define WCOVE_GPIO_NUM (BANK0_NR_PINS + BANK1_NR_PINS +
> BANK2_NR_PINS)
> +#define WCOVE_VGPIO_NUM 94
> +/* GPIO output control registers(one per pin): 0x4e44 - 0x4e50 */
> +#define GPIO_OUT_CTRL_BASE 0x4e44
> +/* GPIO input control registers(one per pin): 0x4e51 - 0x4e5d */
> +#define GPIO_IN_CTRL_BASE0x4e51
> +
> +/*
> + * GPIO interrupts are organized in two groups:
> + * Group 0: Bank 0 pins (Pin 0 - 6)
> + * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
> + * Each group has two registers(one bit per pin): status and mask.
> + */
> +#de
