Re: [PATCH v5 2/2] arm: dts: mt2712: add uart APDMA to device tree

2018-12-12 Thread Yingjoe Chen 
On Tue, 2018-12-11 at 13:37 +0800, Long Cheng wrote:
> 1. add uart APDMA controller device node
> 2. add uart 0/1/2/3/4/5 DMA function
> 
> Signed-off-by: Long Cheng 
> ---
>  arch/arm64/boot/dts/mediatek/mt2712e.dtsi |   50 
> +
>  1 file changed, 50 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
> b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> index 976d92a..a59728b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -300,6 +300,9 @@
>   interrupts = ;
>   clocks = <_clk>, <_clk>;
>   clock-names = "baud", "bus";
> + dmas = < 10
> +  11>;
> + dma-names = "tx", "rx";
>   status = "disabled";
>   };
>  
> @@ -378,6 +381,38 @@
>   status = "disabled";
>   };
>  
> + apdma: dma-controller@11000400 {
> + compatible = "mediatek,mt2712-uart-dma",
> +  "mediatek,mt6577-uart-dma";

Sorting, please make sure this is before 

auxadc: adc@11001000 {


> + reg = <0 0x11000400 0 0x80>,
> +   <0 0x11000480 0 0x80>,
> +   <0 0x11000500 0 0x80>,
> +   <0 0x11000580 0 0x80>,
> +   <0 0x11000600 0 0x80>,
> +   <0 0x11000680 0 0x80>,
> +   <0 0x11000700 0 0x80>,
> +   <0 0x11000780 0 0x80>,
> +   <0 0x11000800 0 0x80>,
> +   <0 0x11000880 0 0x80>,
> +   <0 0x11000900 0 0x80>,
> +   <0 0x11000980 0 0x80>;
> + interrupts = ,
> +  ,
> +  ,
> +  ,
> +  ,
> +  ,
> +  ,
> +  ,
> +  ,
> +  ,
> +  ,
> +  ;
> + clocks = < CLK_PERI_AP_DMA>;
> + clock-names = "apdma";
> + #dma-cells = <1>;
> + };
> +
>   uart0: serial@11002000 {
>   compatible = "mediatek,mt2712-uart",
>"mediatek,mt6577-uart";
> @@ -385,6 +420,9 @@


...deleted

[PATCH v5 2/2] arm: dts: mt2712: add uart APDMA to device tree

2018-12-10 Thread Long Cheng 
1. add uart APDMA controller device node
2. add uart 0/1/2/3/4/5 DMA function

Signed-off-by: Long Cheng 
---
 arch/arm64/boot/dts/mediatek/mt2712e.dtsi |   50 +
 1 file changed, 50 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi 
b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 976d92a..a59728b 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -300,6 +300,9 @@
interrupts = ;
clocks = <_clk>, <_clk>;
clock-names = "baud", "bus";
+   dmas = < 10
+11>;
+   dma-names = "tx", "rx";
status = "disabled";
};
 
@@ -378,6 +381,38 @@
status = "disabled";
};
 
+   apdma: dma-controller@11000400 {
+   compatible = "mediatek,mt2712-uart-dma",
+"mediatek,mt6577-uart-dma";
+   reg = <0 0x11000400 0 0x80>,
+ <0 0x11000480 0 0x80>,
+ <0 0x11000500 0 0x80>,
+ <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>,
+ <0 0x11000680 0 0x80>,
+ <0 0x11000700 0 0x80>,
+ <0 0x11000780 0 0x80>,
+ <0 0x11000800 0 0x80>,
+ <0 0x11000880 0 0x80>,
+ <0 0x11000900 0 0x80>,
+ <0 0x11000980 0 0x80>;
+   interrupts = ,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+,
+;
+   clocks = < CLK_PERI_AP_DMA>;
+   clock-names = "apdma";
+   #dma-cells = <1>;
+   };
+
uart0: serial@11002000 {
compatible = "mediatek,mt2712-uart",
 "mediatek,mt6577-uart";
@@ -385,6 +420,9 @@
interrupts = ;
clocks = <_clk>, <_clk>;
clock-names = "baud", "bus";
+   dmas = < 0
+1>;
+   dma-names = "tx", "rx";
status = "disabled";
};
 
@@ -395,6 +433,9 @@
interrupts = ;
clocks = <_clk>, <_clk>;
clock-names = "baud", "bus";
+   dmas = < 2
+3>;
+   dma-names = "tx", "rx";
status = "disabled";
};
 
@@ -405,6 +446,9 @@
interrupts = ;
clocks = <_clk>, <_clk>;
clock-names = "baud", "bus";
+   dmas = < 4
+5>;
+   dma-names = "tx", "rx";
status = "disabled";
};
 
@@ -415,6 +459,9 @@
interrupts = ;
clocks = <_clk>, <_clk>;
clock-names = "baud", "bus";
+   dmas = < 6
+7>;
+   dma-names = "tx", "rx";
status = "disabled";
};
 
@@ -629,6 +676,9 @@
interrupts = ;
clocks = <_clk>, <_clk>;
clock-names = "baud", "bus";
+   dmas = < 8
+9>;
+   dma-names = "tx", "rx";
status = "disabled";
};
 
-- 
1.7.9.5