Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Anatolij Gustschin]

Hi Matthew,

On Wed, 22 Mar 2017 09:08:18 -0700 (PDT)
matthew.gerl...@linux.intel.com matthew.gerl...@linux.intel.com wrote:
...
>> Can we also add a function for registering a PCIe device with
>> PR IP here? Something like:  
>
>If we have an alt_pr_pcie_register function, we will need the 
>corresponding alt_pr_pcie_unregister function.  Both of these functions 
>should go into their own file like alt_pr_platform_probe() and 
>alt_pr_platform_remove().

Okay, thanks.

>> /**
>> * alt_pr_pcie_register - register PCIe device with PR-IP core
>> * @pci_dev:PCI device with PR-IP
>> * @bar:PR-IP BAR number
>> * @pr_offset:  offset of the PR-IP core registers
>> *
>> * Return: 0 on success, negative error code otherwise.
>> *
>> * To unregister the PCIe device, use alt_pr_unregister(&pdev->dev).
>> */
>> int alt_pr_pcie_register(struct pci_dev *pdev, int bar, int pr_offset)
>> {
>>void __iomem *base;
>>int ret;
>>
>>if (!pci_is_enabled(pdev)) {
>>ret = pci_enable_device(pdev);
>>if (ret < 0) {
>>dev_err(&pdev->dev, "can't enable device: %d\n", ret);
>>return ret;
>>}
>>}
>>
>>base = devm_ioremap_resource(&pdev->dev, &pdev->resource[bar]);  
>
>Does this remap the whole bar?  If it does, what happens if other 
>components are also connected to the bar?  How do those corresponding 
>drivers get access to the mapped memory?

yes, it remaps the whole bar. I do not know the details of the PR IP,
my assumption was that PR IP it is only one component in the bar.
Then I could use devm_ioremap() instead. Thanks for the hint!

Anatolij

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[matthew . gerlach]

On Tue, 21 Mar 2017, Anatolij Gustschin wrote:


Hi Matthew,


Hi Anatolij,



On Fri, 10 Mar 2017 11:40:25 -0800
matthew.gerl...@linux.intel.com matthew.gerl...@linux.intel.com wrote:
...

+int alt_pr_unregister(struct device *dev)
+{
+   dev_dbg(dev, "%s\n", __func__);
+
+   fpga_mgr_unregister(dev);
+
+   return 0;
+}
+EXPORT_SYMBOL_GPL(alt_pr_unregister);


Can we also add a function for registering a PCIe device with
PR IP here? Something like:


If we have an alt_pr_pcie_register function, we will need the 
corresponding alt_pr_pcie_unregister function.  Both of these functions 
should go into their own file like alt_pr_platform_probe() and 
alt_pr_platform_remove().




/**
* alt_pr_pcie_register - register PCIe device with PR-IP core
* @pci_dev:PCI device with PR-IP
* @bar:PR-IP BAR number
* @pr_offset:  offset of the PR-IP core registers
*
* Return: 0 on success, negative error code otherwise.
*
* To unregister the PCIe device, use alt_pr_unregister(&pdev->dev).
*/
int alt_pr_pcie_register(struct pci_dev *pdev, int bar, int pr_offset)
{
   void __iomem *base;
   int ret;

   if (!pci_is_enabled(pdev)) {
   ret = pci_enable_device(pdev);
   if (ret < 0) {
   dev_err(&pdev->dev, "can't enable device: %d\n", ret);
   return ret;
   }
   }

   base = devm_ioremap_resource(&pdev->dev, &pdev->resource[bar]);


Does this remap the whole bar?  If it does, what happens if other 
components are also connected to the bar?  How do those corresponding 
drivers get access to the mapped memory?




   if (IS_ERR(base)) {
   dev_warn(&pdev->dev, "mapping PR-IP BAR failed\n");
   return -ENOMEM;
   }

   return alt_pr_register(&pdev->dev, base + pr_offset);
}
EXPORT_SYMBOL_GPL(alt_pr_pcie_register);

Thanks,
Anatolij
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Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Anatolij Gustschin]

Hi Matthew,

On Fri, 10 Mar 2017 11:40:25 -0800
matthew.gerl...@linux.intel.com matthew.gerl...@linux.intel.com wrote:
...
>+int alt_pr_unregister(struct device *dev)
>+{
>+  dev_dbg(dev, "%s\n", __func__);
>+
>+  fpga_mgr_unregister(dev);
>+
>+  return 0;
>+}
>+EXPORT_SYMBOL_GPL(alt_pr_unregister);

Can we also add a function for registering a PCIe device with
PR IP here? Something like:

/**
 * alt_pr_pcie_register - register PCIe device with PR-IP core
 * @pci_dev:PCI device with PR-IP
 * @bar:PR-IP BAR number
 * @pr_offset:  offset of the PR-IP core registers
 *
 * Return: 0 on success, negative error code otherwise.
 *
 * To unregister the PCIe device, use alt_pr_unregister(&pdev->dev).
 */
int alt_pr_pcie_register(struct pci_dev *pdev, int bar, int pr_offset)
{
void __iomem *base;
int ret;

if (!pci_is_enabled(pdev)) {
ret = pci_enable_device(pdev);
if (ret < 0) {
dev_err(&pdev->dev, "can't enable device: %d\n", ret);
return ret;
}
}

base = devm_ioremap_resource(&pdev->dev, &pdev->resource[bar]);
if (IS_ERR(base)) {
dev_warn(&pdev->dev, "mapping PR-IP BAR failed\n");
return -ENOMEM;
}

return alt_pr_register(&pdev->dev, base + pr_offset);
}
EXPORT_SYMBOL_GPL(alt_pr_pcie_register);

Thanks,
Anatolij

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[matthew . gerlach]

On Sat, 18 Mar 2017, Anatolij Gustschin wrote:


Hi Matthew,



Hi Anatolij,

More good feedback.  See below.



thanks for the patches. Please see some comments below.

On Fri, 10 Mar 2017 11:40:25 -0800
matthew.gerl...@linux.intel.com matthew.gerl...@linux.intel.com wrote:

...

+   if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+   pr_err("%s Partial Reconfiguration flag not set\n", __func__);


please use dev_err() here.

...

+   if (val & ALT_PR_CSR_PR_START) {
+   pr_err("%s Partial Reconfiguration already started\n",


dev_err(), too.


Good catch on both of these pr_err().  dev_err() would be better.


...

+static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+   u32 i;
+
+   for (i = 0; i < info->config_complete_timeout_us; i++) {
+   switch (alt_pr_fpga_state(mgr)) {
+   case FPGA_MGR_STATE_WRITE_ERR:
+   return -EIO;
+
+   case FPGA_MGR_STATE_OPERATING:
+   dev_info(&mgr->dev,
+"successful partial reconfiguration\n");
+   return 0;
+
+   default:
+   break;
+   }
+   udelay(1);
+   }
+   dev_err(&mgr->dev, "timed out waiting for write to complete\n");
+   return -ETIMEDOUT;
+}


we will always get timed out error if info->config_complete_timeout_us
is zero. Can we change to
u32 i = 0;
...
do {
...
} while (info->config_complete_timeout_us > i++);
?


This seems more than reasonable to me.



...

diff --git a/drivers/fpga/altera-pr-ip-core.h b/drivers/fpga/altera-pr-ip-core.h
new file mode 100644
index 000..3810a90
--- /dev/null
+++ b/drivers/fpga/altera-pr-ip-core.h


Should we move this header to include/linux/? We can use register/
unregister functions in other drivers (PCIe) outside drivers/fpga
then.

Thanks,

Anatolij

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Anatolij Gustschin]

Hi Matthew,

thanks for the patches. Please see some comments below.

On Fri, 10 Mar 2017 11:40:25 -0800
matthew.gerl...@linux.intel.com matthew.gerl...@linux.intel.com wrote:

...
>+  if (!(info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
>+  pr_err("%s Partial Reconfiguration flag not set\n", __func__);

please use dev_err() here.

...
>+  if (val & ALT_PR_CSR_PR_START) {
>+  pr_err("%s Partial Reconfiguration already started\n",

dev_err(), too.

...
>+static int alt_pr_fpga_write_complete(struct fpga_manager *mgr,
>+struct fpga_image_info *info)
>+{
>+  u32 i;
>+
>+  for (i = 0; i < info->config_complete_timeout_us; i++) {
>+  switch (alt_pr_fpga_state(mgr)) {
>+  case FPGA_MGR_STATE_WRITE_ERR:
>+  return -EIO;
>+
>+  case FPGA_MGR_STATE_OPERATING:
>+  dev_info(&mgr->dev,
>+   "successful partial reconfiguration\n");
>+  return 0;
>+
>+  default:
>+  break;
>+  }
>+  udelay(1);
>+  }
>+  dev_err(&mgr->dev, "timed out waiting for write to complete\n");
>+  return -ETIMEDOUT;
>+}

we will always get timed out error if info->config_complete_timeout_us
is zero. Can we change to
u32 i = 0;
...
do {
...
} while (info->config_complete_timeout_us > i++);
?

...
>diff --git a/drivers/fpga/altera-pr-ip-core.h 
>b/drivers/fpga/altera-pr-ip-core.h
>new file mode 100644
>index 000..3810a90
>--- /dev/null
>+++ b/drivers/fpga/altera-pr-ip-core.h

Should we move this header to include/linux/? We can use register/
unregister functions in other drivers (PCIe) outside drivers/fpga
then.

Thanks,

Anatolij

Re: [PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[Moritz Fischer]

On Fri, Mar 10, 2017 at 11:40 AM,   wrote:
> From: Matthew Gerlach 
>
> Adding the core functions necessary for a fpga-mgr driver
> for the Altera Partial IP component.  It is intended for
> these functions to be used by the various bus implementations
> like the platform bus or the PCIe bus.
>
> Signed-off-by: Matthew Gerlach 
Reviewed-by: Moritz Fischer 
> ---
> v5:
> Fix comment as suggested by Rob Herring 
> v4:
> v3 patch set mistakenly sent out labeled as v4
> v3:
> s/alt_pr_probe/alt_pr_register/
> s/alt_pr_remove/alt_pr_unregister/
> ---
>  drivers/fpga/Kconfig |   5 +
>  drivers/fpga/Makefile|   1 +
>  drivers/fpga/altera-pr-ip-core.c | 217 
> +++
>  drivers/fpga/altera-pr-ip-core.h |  29 ++
>  4 files changed, 252 insertions(+)
>  create mode 100644 drivers/fpga/altera-pr-ip-core.c
>  create mode 100644 drivers/fpga/altera-pr-ip-core.h
>
> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
> index ce861a2..a46c173 100644
> --- a/drivers/fpga/Kconfig
> +++ b/drivers/fpga/Kconfig
> @@ -63,6 +63,11 @@ config ALTERA_FREEZE_BRIDGE
>   isolate one region of the FPGA from the busses while that
>   region is being reprogrammed.
>
> +config ALTERA_PR_IP_CORE
> +tristate "Altera Partial Reconfiguration IP Core"
> +help
> +  Core driver support for Altera Partial Reconfiguration IP component
> +
>  endif # FPGA
>
>  endmenu
> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
> index 8df07bc..82693d2 100644
> --- a/drivers/fpga/Makefile
> +++ b/drivers/fpga/Makefile
> @@ -9,6 +9,7 @@ obj-$(CONFIG_FPGA)  += fpga-mgr.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
>  obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
>  obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)   += zynq-fpga.o
> +obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
>
>  # FPGA Bridge Drivers
>  obj-$(CONFIG_FPGA_BRIDGE)  += fpga-bridge.o
> diff --git a/drivers/fpga/altera-pr-ip-core.c 
> b/drivers/fpga/altera-pr-ip-core.c
> new file mode 100644
> index 000..738d7d1
> --- /dev/null
> +++ b/drivers/fpga/altera-pr-ip-core.c
> @@ -0,0 +1,217 @@
> +/*
> + * Driver for Altera Partial Reconfiguration IP Core
> + *
> + * Copyright (C) 2016-2017 Intel Corporation
> + *
> + * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
> + *  by Alan Tull 
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along 
> with
> + * this program.  If not, see .
> + */
> +#include "altera-pr-ip-core.h"
> +#include 
> +#include 
> +#include 
> +
> +#define ALT_PR_DATA_OFST   0x00
> +#define ALT_PR_CSR_OFST0x04
> +
> +#define ALT_PR_CSR_PR_STARTBIT(0)
> +#define ALT_PR_CSR_STATUS_SFT  2
> +#define ALT_PR_CSR_STATUS_MSK  (7 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_NRESET   (0 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_PR_ERR   (1 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_CRC_ERR  (2 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_BAD_BITS (3 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_PR_IN_PROG   (4 << ALT_PR_CSR_STATUS_SFT)
> +#define ALT_PR_CSR_STATUS_PR_SUCCESS   (5 << ALT_PR_CSR_STATUS_SFT)
> +
> +struct alt_pr_priv {
> +   void __iomem *reg_base;
> +};
> +
> +static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)
> +{
> +   struct alt_pr_priv *priv = mgr->priv;
> +   const char *err = "unknown";
> +   enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN;
> +   u32 val;
> +
> +   val = readl(priv->reg_base + ALT_PR_CSR_OFST);
> +
> +   val &= ALT_PR_CSR_STATUS_MSK;
> +
> +   switch (val) {
> +   case ALT_PR_CSR_STATUS_NRESET:
> +   return FPGA_MGR_STATE_RESET;
> +
> +   case ALT_PR_CSR_STATUS_PR_ERR:
> +   err = "pr error";
> +   ret = FPGA_MGR_STATE_WRITE_ERR;
> +   break;
> +
> +   case ALT_PR_CSR_STATUS_CRC_ERR:
> +   err = "crc error";
> +   ret = FPGA_MGR_STATE_WRITE_ERR;
> +   break;
> +
> +   case ALT_PR_CSR_STATUS_BAD_BITS:
> +   err = "bad bits";
> +   ret = FPGA_MGR_STATE_WRITE_ERR;
> +   break;
> +
> +   case ALT_PR_CSR_STATUS_PR_IN_PROG:
> +   return FPGA_MGR_STATE_WRITE;
> +
> +   case ALT_PR_CSR_

[PATCH v5 2/4] fpga pr ip: Core driver support for Altera Partial Reconfiguration IP.

[matthew . gerlach]

From: Matthew Gerlach 

Adding the core functions necessary for a fpga-mgr driver
for the Altera Partial IP component.  It is intended for
these functions to be used by the various bus implementations
like the platform bus or the PCIe bus.

Signed-off-by: Matthew Gerlach 
---
v5:
Fix comment as suggested by Rob Herring 
v4:
v3 patch set mistakenly sent out labeled as v4
v3:
s/alt_pr_probe/alt_pr_register/
s/alt_pr_remove/alt_pr_unregister/
---
 drivers/fpga/Kconfig |   5 +
 drivers/fpga/Makefile|   1 +
 drivers/fpga/altera-pr-ip-core.c | 217 +++
 drivers/fpga/altera-pr-ip-core.h |  29 ++
 4 files changed, 252 insertions(+)
 create mode 100644 drivers/fpga/altera-pr-ip-core.c
 create mode 100644 drivers/fpga/altera-pr-ip-core.h

diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index ce861a2..a46c173 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -63,6 +63,11 @@ config ALTERA_FREEZE_BRIDGE
  isolate one region of the FPGA from the busses while that
  region is being reprogrammed.
 
+config ALTERA_PR_IP_CORE
+tristate "Altera Partial Reconfiguration IP Core"
+help
+  Core driver support for Altera Partial Reconfiguration IP component
+
 endif # FPGA
 
 endmenu
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 8df07bc..82693d2 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_FPGA)  += fpga-mgr.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA) += socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10) += socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA)   += zynq-fpga.o
+obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
 
 # FPGA Bridge Drivers
 obj-$(CONFIG_FPGA_BRIDGE)  += fpga-bridge.o
diff --git a/drivers/fpga/altera-pr-ip-core.c b/drivers/fpga/altera-pr-ip-core.c
new file mode 100644
index 000..738d7d1
--- /dev/null
+++ b/drivers/fpga/altera-pr-ip-core.c
@@ -0,0 +1,217 @@
+/*
+ * Driver for Altera Partial Reconfiguration IP Core
+ *
+ * Copyright (C) 2016-2017 Intel Corporation
+ *
+ * Based on socfpga-a10.c Copyright (C) 2015-2016 Altera Corporation
+ *  by Alan Tull 
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see .
+ */
+#include "altera-pr-ip-core.h"
+#include 
+#include 
+#include 
+
+#define ALT_PR_DATA_OFST   0x00
+#define ALT_PR_CSR_OFST0x04
+
+#define ALT_PR_CSR_PR_STARTBIT(0)
+#define ALT_PR_CSR_STATUS_SFT  2
+#define ALT_PR_CSR_STATUS_MSK  (7 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_NRESET   (0 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_ERR   (1 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_CRC_ERR  (2 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_BAD_BITS (3 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_IN_PROG   (4 << ALT_PR_CSR_STATUS_SFT)
+#define ALT_PR_CSR_STATUS_PR_SUCCESS   (5 << ALT_PR_CSR_STATUS_SFT)
+
+struct alt_pr_priv {
+   void __iomem *reg_base;
+};
+
+static enum fpga_mgr_states alt_pr_fpga_state(struct fpga_manager *mgr)
+{
+   struct alt_pr_priv *priv = mgr->priv;
+   const char *err = "unknown";
+   enum fpga_mgr_states ret = FPGA_MGR_STATE_UNKNOWN;
+   u32 val;
+
+   val = readl(priv->reg_base + ALT_PR_CSR_OFST);
+
+   val &= ALT_PR_CSR_STATUS_MSK;
+
+   switch (val) {
+   case ALT_PR_CSR_STATUS_NRESET:
+   return FPGA_MGR_STATE_RESET;
+
+   case ALT_PR_CSR_STATUS_PR_ERR:
+   err = "pr error";
+   ret = FPGA_MGR_STATE_WRITE_ERR;
+   break;
+
+   case ALT_PR_CSR_STATUS_CRC_ERR:
+   err = "crc error";
+   ret = FPGA_MGR_STATE_WRITE_ERR;
+   break;
+
+   case ALT_PR_CSR_STATUS_BAD_BITS:
+   err = "bad bits";
+   ret = FPGA_MGR_STATE_WRITE_ERR;
+   break;
+
+   case ALT_PR_CSR_STATUS_PR_IN_PROG:
+   return FPGA_MGR_STATE_WRITE;
+
+   case ALT_PR_CSR_STATUS_PR_SUCCESS:
+   return FPGA_MGR_STATE_OPERATING;
+
+   default:
+   break;
+   }
+
+   dev_err(&mgr->dev, "encountered error code %d (%s) in %s()\n",
+   val, err, __func__);
+   return ret;
+}
+
+static int alt_pr_fpga_write_init(struct fpga_manager *mgr,
+